tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 288

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17.7
Interrupt Generation
RA000
17.7
17.8
17.8.1
17.8.2
interrupts.
when the SESR<SEF> flag is set.
The TMP89FM82 is provided with the SEI interrupt channels 0 and 1 (INTSEI0 and INTSEI1) for processing SEI
INTSEI0 generates an interrupt pulse when the SESR<MODF> flag is set. INTSEI1 generates an interrupt pulse
The SEI can detect the following four types of system errors:
Interrupt Generation
SEI System Errors
・ Mode fault error: A mode fault error occurs if the SS pin of the master device is driven low.
・ Write collision error: A write collision error occurs if data is written to the SEDR register while a transfer is
・ Overflow error: An overflow error occurs if new data is received in a slave device before the previous data
・ Transfer error: A transfer error occurs if the SS pin of the slave device is driven "H" during data transfer.
fault error occurs, the SEI immediately performs the following operations:
SECR register. Once the SESR<MODF> flag is cleared, the mode setting can be made again.
between the SECLK pin and MOSI pin drivers if two or more devices on the same bus are set as the master at
the same time. (It is not possible to prevent the collision of the MISO pins if the SS pins of two or more slave
devices on the same bus are simultaneously driven low.)
Because the SEDR register is not configured as dual-buffers for sending data, a write to the SEDR register directly
results in writing to the SEI shift register. Therefore, writing to the SEDR register while a transfer is in progress
causes a write collision error.
not be written to the shift register. Because slaves cannot control the timing at which the master starts a transfer,
write collision errors normally occur on slave devices. The master has the right to perform a transfer at any time,
and thus write collision errors do not normally occur on the master side. However, both master and slave SEI
devices are capable of detecting write collision errors.
When the SEI device is set as the master, a mode fault error occurs if the SS pin is driven low. When a mode
The SESR<MODF> flag thus set is automatically cleared by a read of the SESR register and a write to the
When open-drain output mode is selected, this mode fault error function can be used to prevent the collision
A write collision error occurs if an attempt is made to write to the SEDR register while data is being transferred.
In no case is data transfer stopped in the middle, so that the write data which caused a write collision error will
Mode fault error
Write collision error
in progress.
is read. "
・ Clears the SECR<MSTR> bit to 0 to set the SEI device as a slave.
・ Clears the SECR<SEE> bit to 0 to disable SEI operation.
・ Sets the SESR<MODF> flag to 1 to generate an INTSEI0 interrupt pulse.
・ Sets the SECLK and MOSI pins to output "H". (These pins become high-impedance in open-drain
Table 17-6 SEI Interrupt
SEI interrupt channe0 (INTSEI0)
SEI interrupt channel 1 (INTSEI1)
output mode, or "H" level in CMOS output mode.)
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Generates an interrupt pulse when the MODF flag is setI
Generates an interrupt pulse when the SEF flag is setI
TMP89FM82