tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 64

• Manufacturer Part Number: tmp89fm82
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.4
Reset Control Circuit
RA000
2.4.4.7
2.4.4.8
2.4.4.9
ming data need to be reloaded by generating an internal factor reset, such as a system clock reset, and activating
the warm-up operation again.
circuit and power-on reset circuit does not satisfy the characteristic specified in the electric characteristics.
Design the system so that the system will not be damaged in such a case.
has reached a predetermined detection voltage.
memory while it is on standby.
reset, except the power-on reset, the factor which causes a reset can be detected.
set.
factor reset detection status register is clear to "0". IRSTSR<FCLR> is cleared to "0" automatically after
initializing the internal factor reset detection status register.
Note 1: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing
Note 2: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR>
When IRSTSR<TRMDS> is read as "1" in the initialize routine immediately after reset release, the trim-
If IRSTSR<TRMDS> is still set to "1" after repeated reading, the detection voltage of the voltage detection
The voltage detection reset is an internal factor reset that occurs when it is detected that the supply voltage
Refer to "Voltage Detection Circuit".
The flash standby reset is an internal factor reset generated by the reading or writing of data of the flash
Refer to "Flash Memory".
By reading the internal factor reset detection status register IRSTSR after the release of an internal factor
The internal factor reset detection status register is initialized by an external reset input or power-on re-
Set IRSTSR<FCLR> to "1" and write 0x71 to SYSCR4. This enables IRSTSR<FCLR> and the internal
Voltage detection reset
Flash standby reset
Internal factor reset detection status register
noise and other effects.
in NORMAL mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be
enabled at unexpected timing.
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TMP89FM82