tmp89fm82 TOSHIBA Semiconductor CORPORATION, tmp89fm82 Datasheet - Page 35
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tmp89fm82
Manufacturer Part Number
tmp89fm82
Description
8 Bit Microcontroller Tlcs-870/c1 Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP89FM82.pdf
(452 pages)
- Current page: 35 of 452
- Download datasheet (5Mb)
RA000
2.3.3
PLL control register 0
PLL control register 1
(0x0F7E)
(0x0F7F)
PLLCR0
PLLCR1
2.3.3.1
Note 1: Bits 7 to 3 of PLLCR0 are read as "0".
Note 2: Set PLLCR0<PLLOUT> to "1" after making sure that the setting of PLLCR1<LUPFG> becomes "1".
Note 1: Bits 5 to 0 of PLLCR1 are read as "0".
Note 2: PLLCR1<LUPFG> is cleared to "0" by reset, and setting <PLLON> to "0 (PLL stop)".
Note 3: Set PLLCR0<PLLOUT> to "1" after making sure that the setting of PLLCR1<LUPFG> becomes "1".
Functions
peripheral circuits.
clock.
as ports, refer to the chapter of I/O Ports.
POFC<P0FC2> to "1" and then set SYSCR2<XTEN> to "1".
oscillator between the XIN and XOUT pins and between the XTIN and XTOUT pins respectively.
XTIN pins and the XOUT/XTOUT pins are kept open.
Read/Write
Read/Write
Bit Symbol
Bit Symbol
After reset
After reset
The clock generator generates the basic clock for the system clocks to be supplied to the CPU core and
It contains two oscillation circuits: one for the high-frequency clock and the other for the low-frequency
The low-frequency oscillation circuit pins are also used as ports P02 and P03. For the setting to use them
To use ports P02 and P03 as the low-frequency clock oscillation circuits (the XTIN and XTOUT pins), set
The high-frequency (fc) clock and the low-frequency (fs) clock can easily be obtained by connecting an
Clock input from an external oscillator is also possible. In this case, external clocks are applied to the XIN/
Clock generator
LUCSET1:0
PLLOUT
PLLON
LUPFG
PLLON
Selects the rock up count
The PLL output control to PMD cir-
cuit
The PLL operation control
The rock up finish flag
R/W
R
7
0
7
0
-
LUPFG
R
R
6
0
6
0
-
R
R
5
0
5
0
-
-
Page 19
00: 2
01: 2
10: 2
11: 2
0: Output disable
1: Ouput enable
0: Stop
1: Operate
0: Operating rock up
1: Finish rock up
13
12
11
10
(1.024ms, fc=8MHz)
(0.512ms, fc=8MHz)
(0.256ms, fc=8MHz)
(0.128ms, fc=8MHz)
R
R
4
0
4
0
-
-
R
0
R
3
3
0
-
-
LUCSET1
R/W
R
2
0
2
0
-
LUCSET0
R/W
R
1
0
1
0
-
TMP89FM82
PLLOUT
R/W
R
0
0
0
0
-
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