lm9627 National Semiconductor Corporation, lm9627 Datasheet - Page 10

• Manufacturer Part Number: lm9627
• Description: Color Cmos Image Sensor Vga 30 Fps
• Manufacturer: National Semiconductor Corporation

Functional Description
1.0
1.1
The LM9627 contains a CMOS active pixel array consisting of
648 rows by 488 columns. This active region is surrounded by 8
columns and 8 rows of optically shielded (black) pixels as shown
in Figure7.
The color filters are Bayer pattern coded starting at row 8 and
column 8. (rows 0 to 7 & columns 0 to 7 are black). The color
coding is green, red, green, red until the end of row 8, then blue,
green, blue, green until the end or row 9 and so on (see Figure
7).
At the beginning of a given integration time the on-board timing
and control circuit will reset every pixel in the array one row at a
time as shown in Figure 8. Note that all pixels in the same row
are simultaneously reset, but not all pixels in the array.
At the end of the integration time, the timing and control circuit
will address each row and simultaneously transfer the integrated
value of the pixel to a correlated double sampling circuit and
then to a shift register as shown in Figure 8.
Once the correlated double sampled data has been loaded into
the shift register, the timing and control circuit will shift them out
one pixel at a time starting with column “a”.
The pixel data is then fed into an analog video amplifier, where a
user programmed gain is applied (see Figure 9).
After gain adjustment the analog value of each pixel is con-
verted to a 12 bit digital data as shown in Figure 9.
Figure 8: CMOS APS Row and Column addressing scheme
Confidential
8 columns, 8 rows
color (Bayer pattern) active pixels
black pixels
Light Capture and Conversion
OVERVIEW
Figure 7: CMOS APS region of the LM9627
648 columns, 488 rows
Analog Data Out
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
a b c d e f
CDS/Shift Register
g h
8 columns, 8 rows
i
black pixels
j
k l m n o p q r
10
The digital pixel data is further processed to:
• remove defects due to bad pixels,
• compensate black level, before being framed and presented
1.2
The programming, control and status monitoring of the LM9627
is achieved through a two wire I
addition, a slave address pin is provided (see Figure 11).
Additional control and status pins: snapshot and external event
synchronization are provided allowing the latency of the serial
control port to be bypassed during single frame capture. An
interrupt request pin is also available allowing complex snapshot
operations to be controlled via an external micro-processor (see
Figure 12).
Figure 9: Analog Signals Conditioning & Conversion to
on the digital output port. (see Figure 10).
Figure 12. Snapshot & External Event Trigger Signals
Register Bank
Program and Control Interfaces
Figure 11. Control Interface to the LM9627.
Analog pixel values
0-15dB
Figure 10. Digital Pixel Processing.
Video
AMP
Generator
Timing
I
2
Digital
C Compatible
Serial I/F
2
C compatible serial bus. In
12 Bit A/D
Digital pixel data
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snapshot
irq
extsyn
sadr
sda
sclk
vsync
pclk
hsync
do[11:0]