lm9627 National Semiconductor Corporation, lm9627 Datasheet - Page 23

• Manufacturer Part Number: lm9627
• Description: Color Cmos Image Sensor Vga 30 Fps
• Manufacturer: National Semiconductor Corporation

Functional Description
14.6
The sensor’s digital video port’s synchronisation signals can be
programmed to operate in slave mode. In slave mode the inte-
grated timing and control block will only start frame and row pro-
cessing upon the receipt of triggers from an external source.
Only two synchronization signals are used in slave mode as fol-
lows:
Figure 46 shows the LM9627’s digital video port in slave mode
connected to a digital video processor master DVP.
Confidential
hsync
vsync
internal row
Synchronisation Signals in Slave Mode
counter
hsync
mclk
vsync
count
mclk
LM9627
Figure 46. LM9627 in slave mode
is the row trigger input signal.
is the frame trigger input signal.
d[11:0]
hsync
vsync
d[11:0]
hsync
count
mclk
mclk
mclk
pclk
Figure 47. hsync slave mode timing diagram for centred display window of 642 pixels
776
line 502
Figure 48. vsync slave mode timing diagram for scan window of 504 rows.
777
96 clock cycles
778
No more than
776
779
777
0
(continued)
778
din[11:0]
RowTrig
FrameTrig
MasterClock
1
DVP
779
2
780 clock cycles per line
0
3
1
line502
2
...
3
774
...
780 clock cycles per line
775
776
134 135 136 136 137
23
pixel 11
14.7
The row trigger input pin, hsync, is used to trigger the process-
ing of a given row. It must be activated for at least two “ mclk”
cycle. The first pixel data will appear at d[11:0] “X
after the assertion of the row trigger, were X
Where:
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
14.8
The frame trigger input pin, vsync, is used to reset the row
address counter and prepare the array for row processing. It
must be activated for at least one “mclk” cycle and no more than
96 mclk cycles after the activation of hsync as illustrated in Fig-
ure 48.
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
777
778
DW
pixel 12
779
Row Trigger Input Pin (hsync)
Frame Trigger Input Pin (vsync)
StAd
0
642 valid pixels
1
is the value of the display window column start
address.
...
X
mclk
...
774
line503
775
= 124 + DW
774
776
775
777
pixel 652
776
778
777
StAd
779
778
0
779
mclk
1
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0
is given by:
line 0
1
mclk
“periods