lm9627 National Semiconductor Corporation, lm9627 Datasheet - Page 25

• Manufacturer Part Number: lm9627
• Description: Color Cmos Image Sensor Vga 30 Fps
• Manufacturer: National Semiconductor Corporation

Register Set
The following section describes all available registers in the
LM9627 register bank and their function.
Register Name Device Rev Register
Mnemonic
Address
Type
Register Name Main Configuration 0
Address
Mnemonic
Type:
Reset Value
Confidential
7:0
7
6
5
4
3
2:0
Bit
Bit
PwrUpBusy
PwrDown
BPCorrection
BlkLComp
SnapEnable
Bit Symbol
SiRev
Bit Symbol
REV
01 Hex
Read Only.
02 Hex
MCFG0
Read/Write
00 Hex
(Read Only Bit)
Indicates that power on initializa-
tion is in progress. The sensor is
ready for use when this bit is at
logic 0.
Assert to power down the sensor.
Writing a logic 1 to this register bit
has the same effect as taking the
pdwn pin high. Clear (the default)
this bit to power up the sensor.
Assert to enable the bad pixel
detection and correction circuit.
Clear (the default) to switch it off.
Assert to disable the black level
compensation circuit. Clear (the
default) to switch it on.
Assert to enable the external
snapshot pin. Clear (the default)
to disable the external snapshot
pin.
Reserved
The silicon revision register.
Description
Description
25
Register Name Main Configuration 1
Address
Mnemonic
Type
Reset Value
Register Name Power Control Register 1
Address
Mnemonic
Type
Reset Value
7
6
5
4
3
2
1:0
7
6:4
3
2:1
0
Bit
Bit
ByPassGain
PwdnPGA
PwDnADC
ColorMode
ScanMode
HSubSamEn
VSubSamEn
SlaveMode
Bit Symbol
Bit Symbol
03 Hex
MCFG1
Read/Write
00 Hex
04 Hex
PCR
Read/Write
00 Hex
Assert to route the analog video
signal from the output of the CDS
to the input of the 12 bit A/D. Clear
(the default) to route the signal to
the video gain amplifier.
Reserved
Assert to power down the pro-
grammable video gain amplifier.
Clear (the default) to power up the
video gain amplifiers.
Reserved
Assert to power down the 12 bit
analog to digital convertor. Clear
(the default) to power up the 12 bit
analog to digital convertor.
Assert when using a mono-
chrome sensor. When this bit is
at a logic 1, Sub-Sampling is set
to 2:1 and every other row is
read out during interlace mode.
Clear (the default) when using a
color sensor. When this bit is at
logic 0, sub-sampling is set to
4:2 and every other row pair is
read out during interlace mode.
Assert to set the sensor to inter-
lace readout mode. Clear (the
default) to set the sensor to pro-
gressive scan read out mode.
Assert to enable horizontal sub-
sampling. Clear (the default) to
disable horizontal sub-sampling.
Assert to enable vertical sub-
sampling. Clear (the default) to
disable vertical sub-sampling.
Reserved
Use to configure the digital
video port’s synchronisation sig-
nal to operate in slave mode. By
default the digital video’s port’s
synchronization signals are con-
figured to operate in master
mode.
Reserved
Description
Description
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