W83877 Winbond Electronics Corp America, W83877 Datasheet - Page 19

• Manufacturer Part Number: W83877
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

2.1.1 AT interface
The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
2.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
and DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The
advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors.
The following tables give several examples of the delays with a FIFO. The data are based upon the
following formula:
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating
the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK and
addresses need not be valid.
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed
by the FDC based only on DACK . This mode is only available when the FDC has been configured
FIFO THRESHOLD
FIFO THRESHOLD
15 Byte
15 Byte
1 Byte
2 Byte
8 Byte
1 Byte
2 Byte
8 Byte
THRESHOLD #
Data Rate
(1/DATA/RATE) *8 - 1.5 S = DELAY
1
2
8
15
Data Rate
1
2
8
15
MAXIMUM DELAY TO SERVICING AT 500K BPS
MAXIMUM DELAY TO SERVICING AT 1M BPS
16 S - 1.5 S = 30.5 S
16 S - 1.5 S = 6.5 S
8 S - 1.5 S = 6.5 S
8 S - 1.5 S = 14.5 S
8 S - 1.5 S = 62.5 S
16 S - 1.5 S = 14.5 S
16 S - 1.5 S = 238.5 S
8 S - 1.5 S = 118.5 S
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Publication Release Date: January 1996
W83877F
Revision A2