W83877 Winbond Electronics Corp America, W83877 Datasheet - Page 70

• Manufacturer Part Number: W83877
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

After programming of the configuration register is finished, an additional value should be written to
EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
registers. In the case of EFER at 250H, this additional value can be any value other than 88H if
HEFERE = 0 and 89H if HEFERE = 1. While EFER is at 3F0H, this additional value must be AAH.
The designer can also set bit 6 of CR9 (LOCKREG) to high to protect the configuration registers
against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
8.1 Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83877F enters the default operating mode. Before the W83877F enters
the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are
250H or 3F0H (as described in the above section).
8.2 Extended Function Index Registers (EFIRs), Extended Function Data Registers
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (0H, 1H, 2H, ..., or 29H) to access Configuration Register 0 (CR0),
Configuration Register 1 (CR1), Configuration Register 2 (CR2), and so forth through the Extended
Function Data Register (EFDR). The EFIRs are write-only registers with port address 251H or 3F0H
(as described in section 8.0) on PC/AT systems; the EFDRs are read/write registers with port address
252H or 3F1H (as described in section 8.0) on PC/AT systems. The function of each configuration
register is described below.
8.2.1 Configuration Register 0 (CR0), default = 00H
When the device is in Extended Function mode and EFIR is 0H, the CR0 register can be accessed
through EFDR. The bit definitions for CR0 are as follows:
Bit 7-Bit 4: Reserved.
PRTMOD1 PRTMOD0 (Bit 3, Bit 2):
(EFDRs)
7
6
5
4
3
- 70 -
2
1
0
PRTMODS0
OCSS0
OCSS1
PRTMODS1
reserved
reserved
reserved
reserved
W83877F