attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 120

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

12.9.4
120
ATtiny167
Phase Correct PWM Mode
OC1A/B value will only be visible on the port pin if the data direction for the port pin is set as
output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is generated by setting (or
clearing) the OC1A/B Register at the compare match between OCR1A/B and TCNT1, and clear-
ing (or setting) the OC1A/B Register at the timer clock cycle the counter is cleared (changes
from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represents special cases when generating a
PWM waveform output in the fast PWM mode. If the OCR1A/B is set equal to BOTTOM
(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the
OCR1A/B equal to TOP will result in a constant high or low output (depending on the polarity of
the output set by the COM1A/B1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). The waveform
generated will have a maximum frequency of f
(0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer
feature of the Output Compare unit is enabled in the fast PWM mode.
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-
slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1A/B) is
cleared on the compare match between TCNT1 and OCR1A/B while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu-
tion in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on
shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
R
PCPWM
f
OCnxPWM
=
log
---------------------------------- -
(
log
TOP
=
2 ( )
---------------------------------- -
N
+
OC
⋅
1
(
f
)
clk_I/O
1
1
A
+
= f
TOP
clk_I/O
)
/2 when OCR1A is set to zero
Figure
12-9. The figure
7728A–AUTO–07/08