attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 148

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

14.3.5
148
ATtiny167
Start Condition Detector
1. The a start condition is generated by the Master by forcing the SDA low line while the
2. In addition, the start detector will hold the SCL line low after the Master has forced an
3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave
4. After eight bits are transferred containing slave address and data direction (read or
5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given
If the Slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the Master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 14-6. Start Condition Detector, Logic Diagram
The start condition detector is shown in Figure 14-6. The SDA line is delayed (in the range of 50
to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled
in Two-wire mode.
The start condition detector is working asynchronously and can therefore wake up the processor
from the Power-down sleep mode. However, the protocol used might have restrictions on the
SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by
the CKSEL Fuses (see
into the consideration. Refer to the USISIF bit description on page 150 for further details.
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the corresponding bit in the PORT Register to zero. Note that the
USI Data Register bit must be set to one for the output to be enabled. The slave device’s
start detector logic (Figure 14-6.) detects the start condition and sets the USISIF Flag.
The flag can generate an interrupt if necessary.
negative edge on this line (B). This allows the Slave to wake up from sleep or complete
its other tasks before setting up the USI Data Register to receive the address. This is
done by clearing the start condition flag and reset the counter.
samples the data and shift it into the USI Data Register at the positive edge of the SCL
clock.
write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not
the one the Master has addressed, it releases the SCL line and waits for a new start
condition.
before holding the SCL line low again (i.e., the Counter Register must be set to 14 before
releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If
the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line)
The slave can hold the SCL line low after the acknowledge (E).
by the Master (F). Or a new start condition is given.
Write( USISIF)
SDA
SCL
”Clock Systems and their Distribution” on page
D Q
CLR
D Q
CLR
23) must also be taken
USISIF
CLOCK
HOLD
7728A–AUTO–07/08