attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 149

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.5
14.5.1
7728A–AUTO–07/08
Alternative USI Usage
Register Descriptions
Half-duplex Asynchronous Data Transfer
4-bit Counter
12-bit Timer/Counter
Edge Triggered External Interrupt
Software Interrupt
USIDR – USI Data Register
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more
compact and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
• Bits 7:0 – USID7..0: USI Data
When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly. If
a serial clock occurs at the same cycle the register is written, the register will contain the value
written and no shift is performed. A (left) shift operation is performed depending of the
USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a
Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note that
even when no wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and
the external clock input (USCK/SCL) can still be used by the USI Data Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch
to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent)
during the first half of a serial clock cycle when an external clock source is selected
(USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The
output will be changed immediately when a new MSB written as long as the latch is open. The
latch ensures that data input is sampled and data output is changed on opposite clock edges.
Bit
Read/Write
Initial Value
USID7
R/W
7
0
USID6
R/W
6
0
USID5
R/W
5
0
USID4
R/W
4
0
USID3
R/W
3
0
USID2
R/W
2
0
USID1
R/W
1
0
ATtiny167
USID0
R/W
0
0
USIDR
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