attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 172

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

15.5.15.2
15.5.16
172
ATtiny167
OCD Support
UART Data Register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be
for data out and in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
This chapter describes the behavior of the LIN/UART controller stopped by the OCD (i.e. I/O
view behavior in AVR Studio)
1. LINCR:
2. LINSIR:
3. LINENR:
4. LINERR:
5. LINBTR:
6. LINBRRH & LINBRRL:
7. LINDLR:
8. LINIDR:
9. LINSEL:
10. LINDAT:
Note:
- LINCR[6..0] are R/W accessible,
- LSWRES always is a self-reset bit (needs 1 micro-controller cycle to execute)
- LIDST[2..0] and LBUSY are always Read accessible,
- LERR & LxxOK bit are directly accessible (unlike in execution, set or cleared directly by
writing 1 or 0).
- Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR bits.
- All bits are R/W accessible.
- All bits are R/W accessible,
- Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR.
- LBT[5..0] are R/W access only if LDISR is set,
- If LDISR is reset, LBT[5..0] are unchangeable.
- All bits are R/W accessible.
- All bits are R/W accessible.
- LID[5..0] are R/W accessible,
- LP[1..0] are Read accessible and are always updated on the fly.
- All bits are R/W accessible.
- All bits are in R/W accessible,
- Note that LAINC has no more effect on the auto-incrementation and the access to the
full FIFO is done setting LINDX[2..0] of LINSEL.
When a debugger break occurs, the state machine of the LIN/UART controller is stopped
(included frame time-out) and further communication may be corrupted.
7728A–AUTO–07/08