lpc1114fn28/102 NXP Semiconductors, lpc1114fn28/102 Datasheet - Page 37

• Manufacturer Part Number: lpc1114fn28/102
• Description: 32-bit Arm Cortex-m0 Microcontroller; Up To 32 Kb Flash And 8 Kb Sram
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1110_11_12_13_14
Product data sheet
CAUTION
7.17.5 APB interface
7.17.6 AHBLite
7.17.7 External interrupt inputs
7.18 Emulation and debugging
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC111x user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 2 November 2011
Section
7.17.1).
LPC1110/11/12/13/14
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2011. All rights reserved.
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