lpc2939fbd208 NXP Semiconductors, lpc2939fbd208 Datasheet - Page 56

• Manufacturer Part Number: lpc2939fbd208
• Description: Arm9 Microcontroller With Can, Lin, And Usb
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2939_1
Preliminary data sheet
6.16.2.3 Pin description
6.16.3 Clock generation for USB (CGU1)
Triple output phases:
clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks
with a 120 phase difference. In this mode all three clocks generated by the analog
section are sent to the output dividers. When the PLL has not yet achieved lock the
second and third phase output dividers run unsynchronized, which means that the phase
relation of the output clocks is unknown. When the PLL LOCK register is set the second
and third phase of the output dividers are synchronized to the main output clock CLKOUT
PLL, thus giving three clocks with a 120 phase difference.
Direct output mode:
clock is divided by 2, 4, 8 or 16 depending on the value on the PSEL[1:0] input, giving an
output clock with a 50 % duty cycle. If a higher output frequency is needed the CCO clock
can be sent directly to the output by setting DIRECT to logic 1. Since the CCO does not
directly generate a 50 % duty cycle clock, the output clock duty cycle in this mode can
deviate from 50 %.
Power-down control:
consumption when the PLL clock is not needed. This is enabled by setting the PD control
register bit. In this mode the analog section of the PLL is turned off, the oscillator and the
phase-frequency detector are stopped and the dividers enter a reset state. While in
Power-down mode the LOCK output is LOW, indicating that the PLL is not in lock. When
Power-down mode is terminated by clearing the PD control-register bit the PLL resumes
normal operation, and makes the LOCK signal HIGH once it has regained lock on the
input clock.
The CGU0 module in the LPC2939 has the pins listed in
Table 28.
The CGU1 block is functionally identical to the CGU0 block and generates two clocks for
the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and
fractional divider. The PLLs used in CGU0 and CGU1 are identical (see
The clock input to the CGU1 PLL is provided by one of two base clocks generated in the
CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK. The base clock not used for the PLL
can be configured to drive the output clock directly.
Symbol
XOUT_OSC
XIN_OSC
CGU0 pins
In normal operating mode (with DIRECT set to logic 0) the CCO
Direction
OUT
IN
A Power-down mode has been incorporated to reduce power
Rev. 01 — 11 June 2009
For applications that require multiple clock phases two additional
Description
Oscillator crystal output
Oscillator crystal input or external clock input
ARM9 microcontroller with CAN, LIN, and USB
Table 28
below.
LPC2939
© NXP B.V. 2009. All rights reserved.
Section
6.16.2.2).
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