mb95f204h Fujitsu Microelectronics, Inc., mb95f204h Datasheet - Page 40

• Manufacturer Part Number: mb95f204h
• Description: F2mc-8fx Mb95200h/210h Series
• Manufacturer: Fujitsu Microelectronics, Inc.

40
MB95200H/210H Series
(2) Source Clock/Machine Clock
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio selection
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
Source clock
cycle time*
(clock before
division)
Source clock
frequency
Machine clock
cycle time*
(minimum
instruction
execution time)
Machine clock
frequency
bits (SYCC : DIV1 and DIV0) . This source clock is divided to become a machine clock according to the division
ratio set by the machine clock division ratio selection bits (SYCC : DIV1 and DIV0) . In addition, a source clock
can be selected from the following.
Parameter
• Main clock divided by 2
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
• Source clock (no division)
1
2
Symbol
t
t
F
F
F
F
MCLK
SCLK
MPL
SPL
MP
SP
name
Pin
⎯
⎯
⎯
⎯
0.0625
0.031
1.024
3.125
61.5
61.5
Min
0.5
80
80
61
20
⎯
⎯
⎯
⎯
1
16.384
Value
Typ
61
20
50
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(V
16.384
32000
16000
16.25
976.5
16.25
2000
1000
Max
12.5
12.5
320
CC
50
⎯
⎯
⎯
⎯
= 5.0 V ± 10%, V
MHz When the main oscillation clock is used
MHz When the main CR clock is used
MHz When the main oscillation clock is used
MHz When the main CR clock is used
Unit
kHz When the sub-oscillation clock is used
kHz
kHz When the sub-oscillation clock is used
kHz
ns
ns
µs
µs
ns
ns
µs
µs
When the main external clock is used
Min : F
Max : F
When the main CR clock is used
Min : F
Max : F
When the sub-oscillation clock is used
F
When the sub-oscillation clock is used
F
When the sub-CR clock is used
F
When the main oscillation clock is used
Min : F
Max : F
When the main CR clock is used
Min : F
Max : F
When the sub-oscillation clock is used
Min : F
Max : F
When the sub-CR clock is used
Min : F
Max : F
When the sub-CR clock is used
F
CL
CRL
CRL
CRL
= 32.768 kHz, divided by 2
= 100 kHz, divided by 2
= 100 kHz, divided by 2
= 100 kHz
SS
CH
CRH
SP
SP
SPL
SPL
CH
CRH
SP
SP
SPL
SPL
= 0.0 V, T
= 16.25 MHz, no division
= 12.5 MHz
= 32.5 MHz, divided by 2
= 0.5 MHz, divided by 16
= 1 MHz, divided by 16
= 1 MHz, divided by 2
= 16.393 kHz, no division
= 50 kHz, no division
= 12.5 MHz
= 16.393 kHz, divided by 16
= 50 kHz, divided by 16
= 1 MHz
Remarks
A
= − 40 °C to + 85 °C)
DS07-12623-1E