p8x32a Parallax, Inc., p8x32a Datasheet - Page 10

• Manufacturer Part Number: p8x32a
• Description: 8-cog Multiprocessor Microcontroller
• Manufacturer: Parallax, Inc.

Propeller™ P8X32A Datasheet
*Must set corresponding DIR bit to affect pin. A1 = APIN input delayed by 1 clock. A2 = APIN input delayed by 2 clocks. B1 = BPIN input delayed by 1 clock.
4.9.
Each cog has a video generator module that facilitates
transmitting video image data at a constant rate. There are
two registers and one instruction which provide control
and access to the video generator. Counter A of the cog
must be running in a PLL mode and is used to generate
the timing signal for the Video Generator. The Video
Scale Register specifies the number of Counter A PLL
(PLLA) clock cycles for each pixel and number of clock
cycles before fetching another frame of data provided by
the WAITVID instruction which is executed within the cog.
The Video Configuration Register establishes the mode
the Video Generator should operate, and can generate
VGA or composite video (NTSC or PAL).
The Video Generator should be initialized by first starting
Counter A, setting the Video Scale Register, setting the
Copyright © Parallax Inc.
%00000
%00001
%00010
%00011
%00100
%00101
%00110
%00111
%01000
%01001
%01010
%01011
%01100
%01101
%01110
%01111
%10000
%10001
%10010
%10011
%10100
%10101
%10110
%10111
%11000
%11001
%11010
%11011
%11100
%11101
%11110
%11111
CTRMODE
31
-
Video Generator
Counter disabled (off)
PLL internal (video mode)
PLL single-ended
PLL differential
NCO single-ended
NCO differential
DUTY single-ended
DUTY differential
POS detector
POS detector with feedback
POSEDGE detector
POSEDGE detector w/ feedback
NEG detector
NEG detector with feedback
NEGEDGE detector
NEGEDGE detector w/ feedback
LOGIC never
LOGIC !A & !B
LOGIC A & !B
LOGIC !B
LOGIC !A & B
LOGIC !A
LOGIC A <> B
LOGIC !A | !B
LOGIC A & B
LOGIC A == B
LOGIC A
LOGIC A | !B
LOGIC B
LOGIC !A | B
LOGIC A | B
LOGIC always
30..29
VMode
CMode
28
Table 6: Counter Modes (CTRMODE Field Values)
Description
Chroma1
27
Table 7: VCFG Register
Chroma0
26
Page 10 of 36
AuralSub
0 (never)
1 (always)
1
1
1
1
1
1
A
A
A
A
!A
!A
!A
!A
0
!A
A
!B
!A
!A
A
!A
A
A
A
A
B
!A
A
1
25..23
Video Configuration Register, then finally providing data
via the WAITVID instruction. Failure to properly initialize
the Video Generator by first starting PLLA will cause the
cog to indefinitely hang when the WAITVID instruction is
executed.
4.9.1.
The
configuration settings of the video generator and is shown
in Table 7.
In Propeller Assembly, the VMode through AuralSub
fields can conveniently be written using the MOVI
instruction, the VGroup field can be written with the MOVD
instruction, and the VPins field can be written with the
MOVS instruction.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FRQx to PHSx
& !A
& !A
& !B
<> B
& B
== B
| !B
| B
& A
& A
& !B
& B
| !B
| B
Accumulate
1
1
1
1
1
2
2
2
2
1
1
1
1
1
Video
VCFG – Video Configuration Register
22..12
-
Configuration
0 (none)
0
PLLx
PLLx
PHSx[31]
PHSx[31]
PHSx-Carry
PHSx-Carry
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VGroup
11..9
Output*
APIN
Register
8
-
0 (none)
0
0
!PLLx
0
!PHSx[31]
0
!PHSx-Carry
0
!A1
0
!A1
0
!A1
0
!A1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev 1.0 11/14/2007
www.parallax.com
contains
Output*
BPIN
VPins
7..0
the