p8x32a Parallax, Inc., p8x32a Datasheet - Page 13

• Manufacturer Part Number: p8x32a
• Description: 8-cog Multiprocessor Microcontroller
• Manufacturer: Parallax, Inc.

Propeller™ P8X32A Datasheet
4.10.
The CLK register is the System Clock configuration
control; it determines the source and characteristics of the
System Clock. It configures the RC Oscillator, Clock
PLL, Crystal Oscillator, and Clock Selector circuits (See
the Block Diagram, page 1). It is configured at compile
time by the _CLKMODE declaration and is writable at run
time through the CLKSET command. Whenever the CLK
register is written, a global delay of ~75 µs occurs as the
clock source transitions.
Whenever this register is changed, a copy of the value
written should be placed in the Clock Mode value
location (which is BYTE[4] in Main RAM) and the
resulting master clock frequency should be written to the
Clock Frequency value location (which is LONG[0] in
Main RAM) so that objects which reference this data will
have current information for their timing calculations.
Copyright © Parallax Inc.
CLKSEL2
OSCENA
PLLENA
OSCM1
RESET
Name
Bit
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
CLK Register
Always write ‘0’ here unless you intend to reset the chip.
Same as a hardware reset – reboots the chip.
Disables the PLL circuit.
Enables the PLL circuit. The PLL internally multiplies the XIN pin frequency by 16. OSCENA must be ‘1’ to propagate the
XIN signal to the PLL. The PLL’s internal frequency must be kept within 64 MHz to 128 MHz – this translates to an XIN
frequency range of 4 MHz to 8 MHz. Allow 100 µs for the PLL to stabilize before switching to one of its outputs via the
CLKSEL bits. Once the OSC and PLL circuits are enabled and stabilized, you can switch freely among all clock sources by
changing the CLKSEL bits.
Disables the OSC circuit
Enables the OSC circuit so that a clock signal can be input to XIN, or so that XIN and XOUT can function together as a
feedback oscillator. The OSCM bits select the operating mode of the OSC circuit. Note that no external resistors or
capacitors are required for crystals and resonators. Allow a crystal or resonator 10 ms to stabilize before switching to an
OSC or PLL output via the CLKSEL bits. When enabling the OSC circuit, the PLL may be enabled at the same time so that
they can share the stabilization period.
CLKSEL1
OSCM2
RESET
7
0
1
0
1
0
0
1
1
0
0
1
1
CLKSEL0
PLLENA
XOUT Resistance
6
0
1
0
1
0
1
0
1
2000 Ω
1000 Ω
Infinite
500 Ω
OSCENA
Table 14: CLK Register Fields
5
Master Clock
~12 MHz
XIN × 16
~20 kHz
XIN × 1
XIN × 2
XIN × 4
XIN × 8
XIN
Page 13 of 36
XIN and XOUT Capacitance
OSCM1
4
6 pF (pad only)
Effect
Effect
Effect
Use Spin's CLKSET command when possible (see sections
6.3 and 6.4) since it automatically updates all the above-
mentioned locations with the proper information.
36 pF
26 pF
16 pF
Valid Expression
RCFAST
RCSLOW
XINPUT
XTAL1
XTAL2
XTAL3
XINPUT + PLL1X
XINPUT + PLL2X
XINPUT + PLL4X
XINPUT + PLL8X
XINPUT + PLL16X 0_1_1_00_111
OSC+PLL
OSC+PLL
OSC+PLL
OSC+PLL
OSC+PLL
OSCM2
Source
Internal
Internal
OSC
3
Table 13: Valid Clock Modes
CLK Reg. Value Valid Expression CLK Reg. Value
0_0_0_00_000
0_0_0_00_001
0_0_1_00_010
0_0_1_01_010
0_0_1_10_010
0_0_1_11_010
0_1_1_00_011
0_1_1_00_100
0_1_1_00_101
0_1_1_00_110
No external parts (8 to 20 MHz)
No external parts, very low power (13-33 kHz)
DC to 80 MHz Input
4 MHz to 16 MHz Crystal/Resonator
8 MHz to 32 MHz Crystal/Resonator
20 MHz to 60 MHz Crystal/Resonator
OSCENA must be ‘1’
OSCENA and PLLENA must be ‘1’
OSCENA and PLLENA must be ‘1’
OSCENA and PLLENA must be ‘1’
OSCENA and PLLENA must be ‘1’
OSCENA and PLLENA must be ‘1’
CLKSEL2
2
Frequency Range
XTAL1 + PLL1X
XTAL1 + PLL2X
XTAL1 + PLL4X
XTAL1 + PLL8X
XTAL1 + PLL16X 0_1_1_01_111
XTAL2 + PLL1X
XTAL2 + PLL2X
XTAL2 + PLL4X
XTAL2 + PLL8X
XTAL2 + PLL16X 0_1_1_10_111
XTAL3 + PLL1X
XTAL3 + PLL2X
XTAL3 + PLL4X
XTAL3 + PLL8X
XTAL3 + PLL16X 0_1_1_11_111
CLKSEL1
Notes
1
Rev 1.0 11/14/2007
www.parallax.com
0_1_1_01_011
0_1_1_01_100
0_1_1_01_101
0_1_1_01_110
0_1_1_10_011
0_1_1_10_100
0_1_1_10_101
0_1_1_10_110
0_1_1_11_011
0_1_1_11_100
0_1_1_11_101
0_1_1_11_110
CLKSEL0
0