p8x32a Parallax, Inc., p8x32a Datasheet - Page 12

• Manufacturer Part Number: p8x32a
• Description: 8-cog Multiprocessor Microcontroller
• Manufacturer: Parallax, Inc.

Propeller™ P8X32A Datasheet
VGA mode, each 8-bit color value is written to the pins
specified by the VGroup and VPins field. For VGA
typically the 8 bits are grouped into 2 bits per primary
color and Horizontal and Vertical Sync control lines, but
this is up to the software and application of how these bits
are used. For composite video each 8-bit color value is
composed of 3 fields. Bits 0-2 are the luminance value of
the generated signal. Bit 3 is the modulation bit which
dictates whether the chroma information will be generated
and bits 4-7 indicate the phase angle of the chroma value.
When the modulation bit is set to 0, the chroma
information is ignored and only the luminance value is
output to pins. When the modulation bit is set to 1 the
luminance value is modulated ± 1 with a phase angle set
by bits 4-7. In order to achieve the full resolution of the
chroma value, PLLA should be set to 16 times the
modulation frequency (in composite video this is called
the color-burst frequency). The PLLB of the cog is used
to generate the broadcast frequency; whether this is
generated depends on if PLLB is running and the values
of VMode and VPins.
The Pixels parameter describes the pixel pattern to
display, either 16 pixels or 32 pixels depending on the
color depth configuration of the Video Generator. When
four-color mode is specified, Pixels is a 16x2 bit pattern
where each 2-bit pixel is an index into Colors on which
data pattern should be presented to the pins. When two-
color mode is specified, Pixels is a 32x1 bit pattern where
each bit specifies which of the two color patterns in the
lower 16 bits of Colors should be output to the pins. The
Pixel data is shifted out least significant bits (LSB) first.
Copyright © Parallax Inc.
PLLA/PixelClocks
n
Shift by n
Source
Pixels
Figure 4: Video Generator
PLLA/FrameClocks
Page 12 of 36
n
VGroup
When the FrameClocks value is greater than 16 times the
PixelClocks value and 4-color mode is specified, the two
most significant bits are repeated until FrameClocks
PLLA cycles have occurred. When FrameClocks value is
greater than 32 times PixelClocks value and 2-color mode
is specified, the most significant bit is repeated until
FrameClocks PLLA cycles have occurred. When
FrameClocks cycles occur and the cog is not in a WAITVID
instruction, whatever data is on the source and destination
busses at the time will be fetched and used. So it is
important to be in a WAITVID instruction before this
occurs.
While the Video Generator was created to display video
signals, its potential applications are much more diverse.
The Composite Video mode can be used to generate
phase-shift keying communications of a granularity of 16
or less and the VGA mode can be used to generate any bit
pattern with a fully settable and predictable rate.
Figure 4 is a block diagram of how the VGA mode is
organized. The two inverted triangles are the load
mechanism for Pixels and Colors; n is 1 or 2 bits
depending on the value of CMode. The inverted trapezoid
is a 4-way 8-bit multiplexer that chooses which byte of
Colors to output. When in composite video mode the
Modulator transforms the byte into the luminance and
chroma signal and outputs the broadcast signal. VGroup
steers the 8 bits to a block of output pins and outputs to
those pins which are set to 1 in VPins; this combined
functionality is represented by the hexagon.
3
Destination
2
Colors
8
x
1
0
VPins
Modulator
Rev 1.0 11/14/2007
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