p8x32a Parallax, Inc., p8x32a Datasheet - Page 21

• Manufacturer Part Number: p8x32a
• Description: 8-cog Multiprocessor Microcontroller
• Manufacturer: Parallax, Inc.

Propeller™ P8X32A Datasheet
6.4.
The Propeller Assembly Instruction Table lists the instruction’s 32-bit opcode, outputs and number of clock cycles. The
opcode consists of the instruction bits (
(
Z and C flags, if any, is shown in the
(
shows the number of clocks the instruction requires for execution.
Copyright © Parallax Inc.
zcri
R
iiiiii zcri cccc ddddddddd sssssssss
000000 000i 1111 ddddddddd sssssssss
000000 001i 1111 ddddddddd sssssssss
000001 000i 1111 ddddddddd sssssssss
000001 001i 1111 ddddddddd sssssssss
000010 000i 1111 ddddddddd sssssssss
000010 001i 1111 ddddddddd sssssssss
000011 000i 1111 ddddddddd sssssssss
000011 0001 1111 ddddddddd ------000
000011 0011 1111 ddddddddd ------001
000011 0001 1111 ddddddddd ------010
000011 0001 1111 ddddddddd ------011
000011 0011 1111 ddddddddd ------100
000011 0001 1111 ddddddddd ------101
000011 0001 1111 ddddddddd ------110
000011 0001 1111 ddddddddd ------111
000100 001i 1111 ddddddddd sssssssss
000101 001i 1111 ddddddddd sssssssss
000110 001i 1111 ddddddddd sssssssss
000111 001i 1111 ddddddddd sssssssss
001000 001i 1111 ddddddddd sssssssss
001001 001i 1111 ddddddddd sssssssss
001010 001i 1111 ddddddddd sssssssss
001011 001i 1111 ddddddddd sssssssss
001100 001i 1111 ddddddddd sssssssss
001101 001i 1111 ddddddddd sssssssss
001110 001i 1111 ddddddddd sssssssss
001111 001i 1111 ddddddddd sssssssss
010000 001i 1111 ddddddddd sssssssss
010001 001i 1111 ddddddddd sssssssss
010010 001i 1111 ddddddddd sssssssss
010011 001i 1111 ddddddddd sssssssss
010100 001i 1111 ddddddddd sssssssss
010101 001i 1111 ddddddddd sssssssss
010110 001i 1111 ddddddddd sssssssss
010111 001i 1111 ddddddddd sssssssss
010111 000i 1111 --------- sssssssss
) shows the instruction’s default behavior for writing (1) or not writing (0) the instruction’s result value. The
), the conditional execution bits (
Propeller Assembly Instruction Table
0 1
i
d s
?
---
..
Zeros (0) and ones (1) mean binary 0 and 1.
Lower case “i” denotes a bit that is affected by immediate status.
Lower case “d” and “s” indicate destination and source bits.
Question marks denote bits that are dynamically set by the compiler.
Hyphens indicate items that are not applicable or not important.
Double-periods represent a range of contiguous values.
cccc
Z Result
WRBYTE D,S Write D[7..0] to main memory byte S[15..0]
RDBYTE D,S
WRWORD D,S Write D[15..0] to main memory word S[15..1]
RDWORD D,S
WRLONG D,S Write D to main memory long S[15..2]
RDLONG D,S Read main memory long S[15..2] into D
HUBOP
CLKSET D
COGID
COGINIT D
COGSTOP D
LOCKNEW D
LOCKRET D
LOCKSET D
LOCKCLR D
MUL
MULS
ENC
ONES
ROR
ROL
SHR
SHL
RCR
RCL
SAR
REV
MINS
MAXS
MIN
MAX
MOVS
MOVD
MOVI
JMPRET D,S Insert PC+1 into D[8..0] and set PC to S[8..0]
JMP
iiiiii
Instruction
), and the destination and source bits (
and
), the “effect” status for the Z flag, C flag, result and indirect/immediate status
D,S Perform hub operation according to S
D
D,S Multiply unsigned D[15..0] by S[15..0]
D,S Multiply signed D[15..0] by S[15..0]
D,S Encode magnitude of S into D, result = 0..31
D,S Get number of 1's in S into D, result = 0..31
D,S Rotate D right by S[4..0] bits
D,S Rotate D left by S[4..0] bits
D,S Shift D right by S[4..0] bits, set new MSB to 0
D,S Shift D left by S[4..0] bits, set new LSB to 0
D,S Rotate carry right into D by S[4..0] bits
D,S Rotate carry left into D by S[4..0] bits
D,S Shift D arithmetically right by S[4..0] bits
D,S
D,S Set D to S if signed (D < S)
D,S Set D to S if signed (D => S)
D,S Set D to S if unsigned (D < S)
D,S Set D to S if unsigned (D => S)
D,S Insert S[8..0] into D[8..0]
D,S Insert S[8..0] into D[17..9]
D,S Insert S[8..0] into D[31..23]
S
C Result
Read main memory byte S[15..0] into D (0-
extended)
Read main memory word S[15..1] into D (0-
extended)
Set the global CLK register to D[7..0]
Get this cog number (0..7) into D
Initialize a cog according to D
Stop cog number D[2..0]
Checkout a new LOCK number (0..7) into D
Return lock number D[2..0]
Set lock number D[2..0]
Clear lock number D[2..0]
Reverse 32–S[4..0] bottom bits in D and 0-
extend
Set PC to S[8..0]
Page 21 of 36
fields; indicating the meaning of a 1 in those flags. The Result field
Description
ddddddddd
and
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Result = 0
Z Result
D = S
D = S
D = S
D = S
-
-
-
-
-
-
-
-
sssssssss
Unsigned (D < S)
Unsigned (D < S)
Prior lock state
Prior lock state
Signed (D < S)
Signed (D < S)
). The meaning of the
No lock free
No cog free
C Result
D[31]
D[31]
D[31]
D[0]
D[0]
D[0]
D[0]
D[0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Rev 1.0 11/14/2007
www.parallax.com
Clocks
R
0
1
0
1
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Clocks
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
7..22 *
future
future
future
future
field
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4