mc56f801 Freescale Semiconductor, Inc, mc56f801 Datasheet - Page 106

• Manufacturer Part Number: mc56f801
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

10.12 Inter-Integrated Circuit Interface (I
106
1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
2. The maximum t
3. A Fast mode I
4. C
SCL Clock Frequency
Hold time (repeated ) START
condition. After this period, the
first clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START
condition
Data hold time for I
Data set-up time
Rise time of both SDA and SCL
signals
Fall time of both SDA and SCL
signals
Set-up time for STOP condition
Bus free time between STOP and
START condition
Pulse width of spikes that must be
suppressed by the input filter
bridge the undefined region of the falling edge of SCL.
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax
b
= total capacitance of the one bus line in pF.
+ t
SU; DAT
Characteristic
2
C bus device can be used in a Standard mode I
= 1000 + 250 = 1250ns (according to the Standard mode I
HD; DAT
2
C bus devices
has only to be met if the device does not stretch the LOW period (t
Symbol
t
t
t
t
t
HD; STA
HD; DAT
SU; DAT
SU; STO
SU; STA
t
t
f
t
HIGH
LOW
SCL
BUF
t
SP
t
t
r
f
56F8014 Technical Data, Rev. 9
Table 10-17 I
Minimum
250
N/A
4.0
4.7
4.0
4.7
4.0
4.7
0
Standard Mode
0
1
2
C bus system, but the requirement t
2
C Timing
Maximum
3.45
1000
100
300
N/A
2
C bus specification) before the SCL line is released.
2
2
C) Timing
2 +0.1C
2 +0.1C
Minimum
100
1.25
0.6
0.6
0.6
0.6
1.3
0.0
0
LOW
0
1
3
Fast Mode
) of the SCL signal.
b
b
4
4
SU; DAT
IH
min of the SCL signal) to
Maximum
Freescale Semiconductor
0.9
400
300
300
50
> = 250ns must then
2
Preliminary
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
ns