mc56f801 Freescale Semiconductor, Inc, mc56f801 Datasheet - Page 33

• Manufacturer Part Number: mc56f801
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

4.6 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-6
listed in order of the base address.
Freescale Semiconductor
Preliminary
X:$FF FFFF
X:$FF FFFE
X:$FF FFFD
X:$FF FFFC
X:$FF FFFB - X:$FF FFA1
X:$FF FFA0
X:$FF FF9F
X:$FF FF9E
X:$FF FF9D
X:$FF FF9C
X:$FF FF9B
X:$FF FF9A
X:$FF FF99
X:$FF FF98
X:$FF FF97
X:$FF FF96
X:$FF FF95
X:$FF FF94
X:$FF FF93
X:$FF FF92
X:$FF FF91
X:$FF FF90
X:$FF FF8F
X:$FF FF8E
X:$FF FF8D
X:$FF FF8C
X:$FF FF8B
X:$FF FF8A
X:$FF FF89 - X:$FF FF00
summarizes base addresses for the set of peripherals on the 56F8014 device. Peripherals are
Address
OTX1 / ORX1
OTX / ORX (32 bits)
OTXRXSR
OCLSR
OCR
OSCNTR (24 bits)
OSR
OBASE
OTBCR
OTBPR
OTB (21 - 24 bits/stage) Trace Buffer Register Stages
OBCR (24 bits)
OBAR1 (24 bits)
OBAR2 (32 bits)
OBMSK (32 bits)
OBCNTR
OESCR
Register Acronym
Table 4-5 EOnCE Memory Map
56F8014 Technical Data, Rev. 9
Transmit Register Upper Word
Receive Register Upper Word
Transmit Register
Receive Register
Transmit and Receive Status and Control Register
Core Lock / Unlock Status Register
Reserved
Control Register
Instruction Step Counter
Instruction Step Counter
Status Register
Peripheral Base Address Register
Trace Buffer Control Register
Trace Buffer Pointer Register
Trace Buffer Register Stages
Breakpoint Unit Control Register
Breakpoint Unit Control Register
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 2
Breakpoint Unit Address Register 2
Breakpoint Unit Mask Register 2
Breakpoint Unit Mask Register 2
Reserved
EOnCE Breakpoint Unit Counter
Reserved
Reserved
Reserved
External Signal Control Register
Reserved
Register Name
Peripheral Memory Mapped Registers
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