r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 191

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
11.4
11.4.1
Table 11.6
11.4.2
INT0
INT1
INT2
INT3
INT4
After Reset
Pin Name
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 018Eh
The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN
register is to 1 (enabled). The edge polarity is selected using the INTiPL bit in the INTEN register and the POL
bit in the INTiIC register. The input pins used as the INT1 to INT3 input can be selected.
Also, inputs can be passed through a digital filter with three different sampling clocks.
The INT0 pin is shared with the pulse output forced cutoff input of timer RC, and the external trigger input of
timer RB. The INT2 pin is shared with the event input enabled of timer RA.
Table 11.6 lists the Pin Configuration of INT Interrupt.
The INTSR register selects which pin is assigned to the INTi (i = 1 or 3) input. To use INTi, set this register.
Set the INTSR register before setting the INTi associated registers. Also, do not change the setting values in this
register during INTi operation.
Symbol INT3SEL1 INT3SEL0
INT Interrupt
INT1SEL0 INT1 pin select bit
INT1SEL1
INT3SEL0 INT3 pin select bit
INT3SEL1
Bit
Symbol
INTi Interrupt (i = 0 to 4)
INT Interrupt Input Pin Select Register (INTSR)
—
—
—
—
Pin Configuration of INT Interrupt
P4_5
P1_5, P1_7, or P2_0
P6_6
P3_3 or P6_7
P6_5
b7
0
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bits
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Assigned Pin
b6
0
Bit Name
b5
—
0
b4
—
0
Input
Input
Input
Input
Input
b3 b2 b1
Set to 0.
b7 b6
0 0: P1_7 assigned
0 1: P1_5 assigned
1 0: P2_0 assigned
1 1: Do not set.
0 0: P3_3 assigned
0 1: Do not set.
1 0: P6_7 assigned
1 1: Do not set.
I/O
b3
—
0
INT0 interrupt input, timer RB external
trigger input, timer RC pulse output forced
cutoff input
INT1 interrupt input
INT2 interrupt input, timer RA event input
enabled
INT3 interrupt input
INT4 interrupt input
INT1SEL1 INT1SEL0
b2
0
Function
b1
0
Function
b0
—
0
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11. Interrupts
R/W
R/W
R/W
R/W
R/W
R/W
—
—