r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 370

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 20.11
20.4.20 Operating Example
The above applies under the following conditions:
The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 000h by compare match in the TRDGRAi register).
Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output “L” to compare match), the TOCi bit is set to 1 (initial output “H” to compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi “H” output at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi “L” output at TRDGRCi register compare match).
Set bits IOD3 to IOD0 in the TRDIORCi register to 1000b (TRDGRDi register does not control TRDIOBi pin output, pin output at compare match is disabled).
i = 0 or 1
TRDSTR register
TRDSRi register
TRDSRi register
TRDSRi register
TRDIOBi output
TRDIOCi output
TRDIOAi output
Count source
TSTARTi bit in
IMFA bit in
IMFB bit in
IMFC bit in
Value in TRDi register
Operating Example of Output Compare Function
m
m
n
n
p
p
Initial output “H”
Initial output “L”
P+1
Initial output “L”
n+1
m+1
“L” output by compare match
M: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
Set to 0 by a program
“H” output by compare match
Set to 0 by a program
Output inverted by compare match
Set to 0 by a program
m+1
Count
stops
Output level
Output level
Output level
held
held
held
restarts
Count
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20. Timer RD