r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 200

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
As with other maskable interrupts, the timer RC interrupt, timer RD (timer RD0) interrupt, timer RD (timer RD1)
interrupt, synchronous serial communication unit interrupt, I
are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each
interrupt source is generated by a combination of multiple interrupt request sources, the following differences from
other maskable interrupts apply:
•
•
•
•
•
Refer to chapters of the individual peripheral functions (19. Timer RC, 20. Timer RD, 25. Synchronous Serial
Communication Unit (SSU), 26. I
register.
For the interrupt control register, refer to 11.3 Interrupt Control.
When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt
enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested).
When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR
bit is set to 0 (no interrupt requested).
That is, even if the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
retained.
Also, the IR bit is not set to 0 even if 0 is written to this bit.
Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
The IR bit is also not automatically set to 0 when the interrupt is acknowledged.
Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to
set individual bits in the status register to 0.
When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set
to 1, the IR bit remains 1.
When multiple bits in the enable register are set to 1, use the status register to determine which request source
causes an interrupt.
2
C bus Interface, and 32. Flash Memory) for the status register and enable
2
C bus interface interrupt, and flash memory interrupt
Page 168 of 740
11. Interrupts