r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 669

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 32.2
FMSTP Bit (Flash Memory Stop Bit)
CMDRST Bit (Erase/Write Sequence Reset Bit)
CMDERIE Bit (Erase/Write Error Interrupt Enable Bit)
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Write to the FMSTP bit by a program transferred to the RAM.
To reduce the power consumption further in high-speed on-chip oscillator mode, low-speed on-chip oscillator
mode (XIN clock stopped), and low-speed clock mode (XIN clock stopped), set the FMSTP bit to 1. Refer to
33.2.10 Stopping Flash Memory for details.
When entering stop mode or wait mode while CPU rewrite mode is disabled, the FMR0 register does not need
to be set because the power for the flash memory is automatically turned off and is turned back on when exiting
stop or wait mode.
When the FMSTP bit is set to 1 (including during the busy status (the period while the FST7 bit is 0)
immediately after the FMSTP bit is changed from 1 to 0), do not set to low-current-consumption read mode at
the same time.
This bit is used to initialize the flash memory sequence and forcibly stop a program or block erase command.
The program ROM area can be read when resetting the sequence of programming/erasing the data flash area.
If the program or block erase command is forcibly stopped using the CMDRST bit in the FMR0 register,
execute the clear status register command after the FST7 bit in the FST register is changed to 1 (ready). To
program to the same address again, execute the block erase command again and ensure it has been completed
normally before programming. If the addresses and blocks which the program or block erase command is
forcibly stopped are allocated in the program area, set the FMR13 bit in the FMR1 register to 1 (lock bit
disabled) before executing the block erase command again.
When the CMDRST bit is set to 1 (erasure/writing stopped) during erase-suspend, the suspend status is also
initialized. Thus execute block erasure again to the block which the block erasure is being suspended.
When td(CMDRST-READY) has elapsed after the CMDRST bit is set to 1 (erasure/writing stopped), the
executing command is forcibly stopped and reading from the flash memory is enabled.
This bit enables a flash command error interrupt to be generated if the following errors occur:
•
•
•
•
If the CMDERIE bit is set to 1 (erase/write error interrupt enabled), an interrupt is generated if the above errors
occur.
If a flash command error interrupt is generated, execute the clear status register command during interrupt
handling.
To change the CMDERIE bit from 0 (erase/write error interrupt disabled) to 1 (erase/write error interrupt
enabled),
make the setting as follows:
(1) Execute the clear status register command.
(2) Set the CMDERIE bit to 1.
Program error
Block erase error
Command sequence error
Block blank check error
FMSTP bit
Transition to Low-Current-Consumption Read Mode
FST7 bit
Do not set to low-current-consumption read mode.
0 (busy)
Low-current-consumption
read mode enabled
1 (ready)
32. Flash Memory
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