cop87l88gw National Semiconductor Corporation, cop87l88gw Datasheet
cop87l88gw
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cop87l88gw Summary of contents
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... COP87L88GW One-Time Programmable (OTP) Microcontroller General Description The COP87L88GW is a member of the COP8 microcontroller family It is pin and software compatible to the mask ROM COP888GW product family Features Low cost 8-bit microcontroller Y Fully static CMOS with low current drain Y Two power saving modes HALT and IDLE ...
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... The devices operate over a voltage range – High throughput is achieved with an efficient regular instruction set operating at a maximum per instruction rate Top View Order Number COP87L88GWV-XE See NS Plastic Chip Package Number V68A FIGURE 2 Connection Diagram 12527– 2 ...
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Absolute Maximum Ratings SuppIy Voltage ( Voltage at Any Pin Total Current into V Pin (Source) CC Total Current out of GND Pin (Sink) Storage Temperature Range Electrical ...
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AC Electrical Characteristics Parameter Instruction Cycle Time ( Crystal Resonator Ceramic CKI Clock Duty Cycle (Note 6) Rise Time (Note 6) Fall Time (Note 6) Inputs t SETUP t HOLD Output Propagation Delay (Note PD1 ...
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Pin Descriptions V and GND are the power supply pins All V CC pins must be connected CKI is the clock input This comes from a crystal oscillator (in conjunction with CKO) See Oscillator Description sec- tion RESET is the ...
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Pin Descriptions (Continued) Since input only pin and G7 is dedicated CKO clock output pin the associated bits in the data and configuration registers for G6 and G7 are used for special purpose func- tions as outlined ...
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Data Memory Segment RAM Extension The data store memory is either addressed directly by a single-byte address within the instruction or indirectly rela- tive to the reference of the pointers (each con- tains a single-byte address) ...
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Reset This device enters a reset state immediately upon detecting a logic low on the RESET pin The RESET pin must be held low for a minimum of one instruction cycle to guarantee a valid reset During power-up initialization the ...
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Oscillator Circuits (Continued) Table I shows the component values required for various standard crystal values TABLE I CrystaI Oscillator Configuration CKI Freq ( (pF) (pF) (MHz 30– ...
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Timers The device contains a very versatile set of timers (T0 T1 T2) All timers and associated autoreload capture registers power up containing random data TIMER T0 (IDLE TIMER) The device supports applications that require maintaining reaI time and Iow ...
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Timers (Continued) FIGURE 9 Timer in External Event Counter Mode In this mode the input pin TxB can be used as an indepen- dent positive edge sensitive interrupt input if the TxENB control flag is set The occurrence of a ...
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Timers (Continued) TIMER CONTROL FLAGS The timers T1 and T2 have identical control structures The control bits and their functions are summarized below TxC0 Timer Start Stop control in Modes 1 and 2 (Proc- essor Independent PWM and External Event ...
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Timers (Continued) FIGURE 11 Capture Timer 1 Block Diagram The registers shown in the block diagram include those for Capture Timer 1 (CM1) as well as the capture timer 1 con- trol register These registers are read writable (with the ...
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Timers (Continued) The CCMR2 Register Bits are CM2RUN CM2 start stop control bit (1 start 0 CM2IEN CM2 interrupt enable control bit (1 CM2IP1 CM2 interrupt pending bit 1 (1 flowed) CM2IP2 CM2 interrupt pending bit 2 (1 CM2EC Select ...
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Timers (Continued) INITIALIZATION The user should perform the following initialization prior to starting the capture timer 1 Reset the CMxRUN bit 2 Configure the corresponding Port bits as inputs 3 Set the edge control bits CMxEC 4 Reset CMxIP1 (CMxIP1 ...
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Pulse Train Generators (Continued) The four 8-bit registers shown in each individual counter in the block diagram constitute a 16-bit prescaler and a 16-bit count register These registers are all read writable and may be accessed through the data memory ...
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Pulse Train Generators (Continued) The underflow of the counter register produces the signal UFL3 This signal stops the counter by resetting the counter start stop bit and sets the counter interrupt pending flag If the counter interrupt is enabled an ...
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Multiply Divide (Continued) Multiplication Assignment Register Name (Address) Before Operation MDR1 (xx98) Unused MDR2 (xx99) Multiplier MDR3 (xx9A) MDR4 (xx9B) Low byte of multiplicand MDR5 (xx9C) High byte of multiplicand http www national com TABLE III Multiply Divide Registers After ...
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Multiply Divide (Continued) CONTROL REGISTER BITS The Multiply Divide control register (MDCR) is located at address xx9D It has the following bit assignments MULT Start Multiplication Operation (1 e DIV Start Division Operation (1 start) e DIVOVF Division Overflow (if ...
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Power Save Modes (Continued) As with the HALT mode the device can be returned to nor- mal operation with a reset or with a Multi-Input Wake up from the L Port Alternately the microcontroller resumes normal operation from the IDLE ...
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Multi-Input Wakeup (Continued) The Multi-Input Wake Up feature utilizes the L Port The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes The selection is ...
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UART The device contains a full-duplex software programmable UART The UART ( Figure 15 ) consists of a transmit shift register a receive shift register and seven addressable reg- isters as follows a transmit buffer register (TBUF) a receiv- er ...
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UART (Continued) UART CONTROL AND STATUS REGISTERS The operation of the UART is programmed through three registers ENU ENUR and ENUI The function of the individ- ual bits in these registers is as follows ENU-UART Control and Status Register (Address ...
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UART (Continued) ERI This bit enables disables interrupt from the receiver section ERI 0 Interrupt from the receiver is disabled e ERI 1 Interrupt from the receiver is enabled e XTCLK This bit selects the clock source for the transmitter ...
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UART Operation (Continued) For any of the above framing formats the last Stop bit can be programmed 8th of a bit in length If two Stop bits are selected and the 7 8th bit is set (selected) ...
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Baud Clock Generation FIGURE 18 UART BAUD Clock Divisor Registers http www national com (Continued) FIGURE 17 UART BAUD Clock Generation 12527– 12527 – 19 ...
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Baud Clock Generation (Continued) As shown in Table V a Prescaler Factor of 0 corresponds to NO CLOCK This condition is the UART power down mode where the UART clock is turned off for power saving pur- pose The user ...
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Baud Clock Generation As an example considering Asynchronous Mode and a CKI clock of 4 608 MHz the prescaler factor selected is 4 608 1 8432 The 2 5 entry is available in Table V The 1 ...
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Interrupts The device supports a vectored interrupt scheme It sup- ports a total of fourteen interrupt sources Table VI lists all the possible device interrupt sources their arbitration rank- ings and the memory locations reserved for the interrupt vector for ...
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Interrupts (Continued) VIS and the vector table must be located in the same 256-byte block (0y00 to 0yFF) except if VIS is located at the last address of a block In this case the table must be in the next ...
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Detection of Illegal Conditions The device can detect various illegal conditions resulting from coding errors transient noise power supply voltage drops runaway programs etc Reading of undefined ROM gets zeroes The opcode for software interrupt the program ...
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MICROWIRE PLUS (Continued) MICROWIRE PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE PLUS to start shifting the data It gets reset when eight data bits have been shifted The user may reset the BUSY bit ...
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Memory Map All RAM ports and registers (except A and PC) are mapped into data memory address space ADDRESS S ADD REG 0000 to 006F 0070 to 007F xx80 to xx8F xx90 xx91 xx92 xx93 xx94 xx95 xx96 xx97 xx98 ...
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Memory Map (Continued) ADDRESS S ADD REG xxBB xxBC xxBD xxBE xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxC8 xxC9 xxCA xxCB xxCC xxCD to xxCF xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxDA xxDB ...
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Addressing Modes There are ten addressing modes six for operand address- ing and four for transfer of control OPERAND ADDRESSING MODES Register Indirect This is the ‘‘normal’’ addressing mode The operand is the data memory addressed by the B pointer ...
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INSTRUCTION SET ADD A MemI ADD ADC A Meml ADD with Carry SUBC A Meml Subtract with Carry AND A Meml Logical AND ANDSZ A lmm Logical AND lmmed Skip if Zero OR A Meml Logical OR XOR A Meml ...
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Instruction Execution Time Most instructions are single byte (with immediate addressing mode instructions taking two bytes) Most single byte instructions take one cycle time to execute See the BYTES and CYCLES per INSTRUCTION table for details Bytes and Cycles per ...
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Bits 3 – ...
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... These parts include National’s COP8 Assembler Linker Librarian Package (COP8-DEV-IBMA) Probe Card Ordering Information Part Number Package MHW-888GW68PWPC 68 PLCC 2 5V– COP87L88GW MHW-888GW68P5PC 68 PLCC 4 5V– COP87L88GW MACRO CROSS ASSEMBLER National Semiconductor offers a COP8 macro cross assem- bler It runs on industry standard compatible PCs and sup- ...
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Development Support (Continued) PROGRAMMING SUPPORT COP8 –EPU Programming of these OTP devices is supported by the Me- taLink iceMASTER COP8 Evaluation and Programming Unit (COP8 –EPU) The COP8 –EPU is a low cost unit which can be used to program ...
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41 http www national com ...
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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Leaded Chip Carrier (V) Order Number COP87L88GWV- critical component is any component of a life ...