cop87l88gw National Semiconductor Corporation, cop87l88gw Datasheet - Page 23

• Manufacturer Part Number: cop87l88gw
• Description: One-time Programmable Otp Microcontroller
• Manufacturer: National Semiconductor Corporation

UART
UART CONTROL AND STATUS REGISTERS
The operation of the UART is programmed through three
registers ENU ENUR and ENUI The function of the individ-
ual bits in these registers is as follows
ENU-UART Control and Status Register (Address at 0BA)
ENUR-UART Receive Control and Status Register (Address
at 0BB)
ENUI-UART Interrupt and Clock Source Register (Address
at 0BC)
0
1
R
RW Bit is read write
D
DESCRIPTION OF UART REGISTER BITS
ENU UART CONTROL AND STATUS REGISTER
TBMT This bit is set when the UART transfers a byte of
data from the TBUF register into the TSFT register for trans-
mission It is automatically reset when software writes into
the TBUF register
RBFL This bit is set when the UART has received a com-
plete character and has copied it into the RBUF register It
is automatically reset when software reads the character
from RBUF
ERR This bit is a global UART error flag which gets set if
any or a combination of the errors (DOE FE PE) occur
CHL1 CHL0 These bits select the character frame format
Parity is not included and is generated verified by hardware
CHL1
CHL1
CHL1
CHL1
0RW
DOE
STP2
Bit 7
PEN
Bit 7
0RD
Bit 7
0RW
Bit is not used
Bit is cleared on reset
Bit is set to one on reset
Bit is read-only it cannot be written by software
Bit is cleared on read when read by software as a
one it is cleared automatically Writing to the bit does
not affect its state
e
e
e
e
0RD
PSEL1
STP78
0RW
FE
0RW
0 CHL0
0 CHL0
1 CHL0
1 CHL0
(Continued)
0RD
PE
XBIT9
PSEL0
ETDX
0RW
0RW
e
e
e
e
SPARE
0 The frame contains eight data bits
1 The frame continues seven data
0 The frame continues nine data bits
1 Loopback Mode selected Transmit-
0RW
bits
ter output internally looped back to
receiver input Nine bit framing for-
mat is used
SSEL
0RW
CHL1
0RW
RBlT9
XRCLK
0R
0RW
CHL0
0RW
ATTN
0RW
ERR
XTCLK
0R
0RW
XMTG
RBFL
0R
0R
0RW
ERI
RCVG
TBMT
Bit 0
Bit 0
0RW
0R
Bit 0
IR
ETI
23
XBIT9 PSEL0 Programs the ninth bit for transmission
when the UART is operating with nine data bits per frame
For seven or eight data bits per frame this bit in conjunction
with PSEL1 selects parity
PSEL1 PSEL0 Parity select bits
PSEL1
PSEL1
PSEL1
PSEL1
PEN This bit enables disables Parity (7- and 8-bit modes
only)
PEN
PEN
ENUR UART RECEIVE CONTROL AND STATUS
REGISTER
RCVG This bit is set high whenever a framing error occurs
and goes low when RDX goes high
XMTG This bit is set to indicate that the UART is transmit-
ting It gets reset at the end of the last frame (end of last
Stop bit)
ATTN ATTENTION Mode is enabled while this bit is set
This bit is cleared automatically on receiving a character
with data bit nine set
RBIT9 Contains the ninth data bit received when the UART
is operating with nine data bits per frame
SPARE Reserved for future use
PE Flags a Parity Error
PE
PE
FE Flags a Framing Error
FE
FE
DOE Flags a Data Overrun Error
DOE
DOE
ENUI UART INTERRUPT AND CLOCK SOURCE
REGISTER
ETI This bit enables disables interrupt from the transmitter
section
ETI
ETI
e
e
e
e
e
e
e
e
e
e
0 Indicates no Framing Error has been detected
1 Indicates the occurrence of a Framing Error
0 Indicates no Parity Error has been detected since
1 Indicates the occurrence of a Parity Error
0 Interrupt from the transmitter is disabled
1 Interrupt from the transmitter is enabled
e
e
e
e
0 Parity disabled
1 Parity enabled
0 Indicates no Data Overrun Error has been detect-
1 Indicates the occurrence of a Data Overrun Error
the last time the ENUR register was read
since the last time the ENUR register was read
0 PSEL0
0 PSEL1
1 PSEL0
1 PSEL1
ed since the last time the ENUR register was
read
e
e
e
e
0 Odd Parity (if Parity enabled)
1 Odd Parity (if Parity enabled)
0 Mark(1) (if Parity enabled)
1 Space(0) (if Parity enabled)
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