ata5773 ATMEL Corporation, ata5773 Datasheet - Page 167

• Manufacturer Part Number: ata5773
• Description: Microcontroller With Uhf Ask/fsk Transmitter
• Manufacturer: ATMEL Corporation

13.3
13.3.1
8006G–AVR–01/08
Register Description
GTCCR – General Timer/Counter Control Register
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by
hardware, and the Timer/Counter start counting.
PSR10
clk
Bit
0x23 (0x43)
Read/Write
Initial Value
T0
I/O
1. The synchronization logic on the input pins (
Synchronization
TSM
R/W
7
0
ExtClk
R
6
–
0
< f
Clear
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
R
4
–
0
T0)
is shown in
R
3
–
0
R
2
–
0
Figure 13-1 on page
ATtiny24/44/84
clk
T0
R
1
–
0
PSR10
clk_I/O
R/W
0
0
114.
/2.5.
GTCCR
115