ata5773 ATMEL Corporation, ata5773 Datasheet - Page 81

• Manufacturer Part Number: ata5773
• Description: Microcontroller With Uhf Ask/fsk Transmitter
• Manufacturer: ATMEL Corporation

6.3
6.3.1
6.4
6.5
6.5.1
8006G–AVR–01/08
System Clock Prescaler
Clock Output Buffer
Register Description
Switching Time
OSCCAL – Oscillator Calibration Register
The ATtiny24/44/84 system clock can be divided by setting the
ter” on page
requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
and clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. Note that the clock will not be output during reset and that the normal
operation of the I/O pin will be overridden when the fuse is programmed. Any clock source,
including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the
System Clock Prescaler is used, it is the divided system clock that is output.
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value is
automatically written to this register during chip reset, giving the Factory calibrated frequency as
specified in
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
2 on page
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
Bit
0x31 (0x51)
Read/Write
Initial Value
FLASH
178. Calibration outside that range is not guaranteed.
Table 20-2 on page
are divided by a factor as shown in
30. This feature can be used to decrease power consumption when the
CAL7
R/W
7
CAL6
R/W
6
178. The application software can write this register to change
Device Specific Calibration Value
CAL5
R/W
5
CAL4
R/W
4
Table 6-11 on page
CAL3
R/W
3
CAL2
R/W
2
“CLKPR – Clock Prescale Regis-
ATtiny24/44/84
31.
CAL1
R/W
1
I/O
CAL0
R/W
, clk
0
ADC
Table 20-
OSCCAL
, clk
CPU
29
,