xr16m654 Exar Corporation, xr16m654 Datasheet - Page 57

• Manufacturer Part Number: xr16m654
• Description: 1.62v To 3.63v Quad Uart With 64-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.0
GENERAL DESCRIPTION................................................................................................ 1
PIN DESCRIPTIONS ........................................................................................................ 5
1.0 PRODUCT DESCRIPTION .................................................................................................................... 11
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 12
3.0 UART INTERNAL REGISTERS............................................................................................................. 26
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 28
F
A
ORDERING INFORMATION
EATURES
PPLICATIONS
2.1 CPU INTERFACE .............................................................................................................................................. 12
2.2 DEVICE RESET ................................................................................................................................................. 13
2.3 CHANNEL SELECTION .................................................................................................................................... 13
2.4 CHANNELS A-D INTERNAL REGISTERS ....................................................................................................... 14
2.5 INT OUPUTS FOR CHANNELS A-D................................................................................................................. 14
2.6 DMA MODE ....................................................................................................................................................... 14
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 15
2.8 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 15
2.9 TRANSMITTER.................................................................................................................................................. 17
2.10 RECEIVER ....................................................................................................................................................... 19
2.11 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 20
2.12 AUTO RTS HYSTERESIS ............................................................................................................................... 20
2.13 AUTO CTS FLOW CONTROL......................................................................................................................... 21
2.14 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 22
2.15 SPECIAL CHARACTER DETECT.................................................................................................................. 22
2.16 INFRARED MODE ........................................................................................................................................... 23
2.17 SLEEP MODE WITH AUTO WAKE-UP .......................................................................................................... 24
2.18 INTERNAL LOOPBACK................................................................................................................................. 24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 28
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 28
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 28
F
F
F
F
F
T
T
T
T
T
F
F
T
F
F
F
F
T
F
T
F
F
T
T
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
ABLE
IGURE
IGURE
ABLE
ABLE
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 17
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 18
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 18
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 19
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 28
1: C
2: C
3: INT P
4: INT P
5: TXRDY#
6: T
7: A
8: A
9: UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 26
10: INTERNAL REGISTERS DESCRIPTION. S
1. XR16M654 B
2. P
3. P
4. P
5. XR16M654 T
6. T
7. B
8. T
9. T
10. R
11. R
12. A
13. I
14. I
.................................................................................................................................................... 1
YPICAL DATA RATES WITH A
HANNEL
HANNEL
UTO
UTO
YPICAL
RANSMITTER
RANSMITTER
IN
IN
IN
AUD
NFRARED
NTERNAL
UTO
ECEIVER
ECEIVER
.............................................................................................................................................. 1
O
O
O
IN
IN
RTS (H
X
UT
UT
UT
R
ON
O
O
RTS
ATE
A-D S
A-D S
AND
C
A
A
A
PERATION FOR
PERATION FOR
/X
RYSTAL
SSIGNMENT
SSIGNMENT
SSIGNMENT
L
OFF
T
O
O
G
OOP
ARDWARE
AND
RANSMIT
RXRDY# O
YPICAL
PERATION IN NON
PERATION IN
LOCK
ENERATOR
O
O
ELECT IN
ELECT IN
............................................................................................................................... 5
PERATION IN NON
PERATION IN
(S
CTS F
B
C
OFTWARE
ACK IN
D
ONNECTIONS
I
IAGRAM
NTEL
D
F
F
F
) F
OR
OR
OR
ATA
T
R
16 M
68 M
LOW
............................................................................................................................................... 16
UTPUTS IN
LOW
RANSMITTER FOR
ECEIVER FOR
C
FIFO
/M
100-
68-
48-
24 MH
) F
HANNELS
E
FIFO
OTOROLA
C
.......................................................................................................................................... 1
ODE
ODE
NCODING AND
C
-FIFO M
LOW
PIN
PIN
ONTROL
TABLE OF CONTENTS
ONTROL
PIN
AND
-FIFO M
.................................................................................................................................. 15
Z CRYSTAL OR EXTERNAL CLOCK AT
PLCC P
QFN P
................................................................................................................................. 13
................................................................................................................................. 13
AND
C
QFP P
FIFO
A
ONTROL
A - D ................................................................................................................... 25
UTO
D
C
ODE
O
F
........................................................................................................................ 20
ATA
HANNELS
LOW
PERATION
ACKAGE AND
ODE
AND
ACKAGES
ACKAGES
C
RTS F
.................................................................................................................. 19
R
HANNELS
B
ECEIVE
C
.............................................................................................................. 18
............................................................................................................... 22
US
DMA M
HADED BITS ARE ENABLED WHEN
ONTROL
I
LOW
A-D ................................................................................................. 14
NTERCONNECTIONS
....................................................................................................... 21
1
I
I
D
N
N
A-D ........................................................................................... 14
ODE FOR
80-
ATA
C
16
16
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
M
ONTROL
ODE
PIN
AND
AND
D
ECODING
LQFP P
..................................................................................... 18
68 M
68 M
C
M
HANNELS
ODE
ODE
ODE AND
.......................................................................... 12
16X S
.......................................................................... 23
ACKAGE
....................................................................... 20
....................................................................... 2
A-D ........................................................... 15
AMPLING
64-
............................................................... 4
EFR B
PIN
LQFP P
................................................... 17
IT
-4=1 ....................................... 27
ACKAGES
XR16M654/654D
......................... 3