xr16v2752il Exar Corporation, xr16v2752il Datasheet - Page 34

• Manufacturer Part Number: xr16v2752il
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16V2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
EMSR[5:4]: Extended RTS Hysteresis
EMSR[6]: LSR Interrupt Mode
•
•
EMSR[7]: 16X Sampling Rate Mode
Logic 0 = 8X Sampling Rate.
Logic 1 = 16X Sampling Rate (default).
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is
not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD/16 to achieve the fractional baud rate divisor. DLD must be enabled
via EFR bit-4 before it can be accessed.
FRACTIONAL DIVISOR” ON PAGE 10.
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
4.11
4.12
4.13
Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an
interrupt when the character with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
FIFO Level Register (FLVL) - Read-Only
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
Alternate Function Register (AFR) - Read/Write
for details.
EMSR
B
IT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-5
T
ABLE
EMSR
B
IT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
-4
13: A
SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
FCTR
B
UTO
IT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
-1
34
RTS H
FCTR
B
IT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
YSTERESIS
-0
(C
H
HARACTERS
YSTERESIS
RTS#
±16
±24
±32
±40
±44
±48
±52
±12
±20
±28
±36
±4
±6
±8
±8
0
)
REV. 1.0.2