xr16c2550ip Exar Corporation, xr16c2550ip Datasheet - Page 12

• Manufacturer Part Number: xr16c2550ip
• Description: Dual Uart With 16-byte Transmit And Receive Fifos
• Manufacturer: Exar Corporation

XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.10
2.9.3
Receiver
Transmitter Operation in FIFO Mode
F
IGURE
F
IGURE
16X Clock
8. T
16X Clock
7. T
RANSMITTER
Data
Byte
RANSMITTER
Data Byte
Transmit Shift Register (TSR)
O
PERATION IN
O
PERATION IN NON
Transm it Data Shift Register
Transmit
Register
Holding
(THR)
Transm it FIFO
FIFO M
(TSR)
THR
12
-FIFO M
ODE
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
THR Interrupt (ISR bit-1) when TX
FIFO becom es em pty. FIFO is
enabled by FCR bit-0=1.
ODE
M
S
B
TXNOFIFO1
L
S
B
T XFIF O 1
xr
REV. 1.0.1