xr16c2550ip Exar Corporation, xr16c2550ip Datasheet - Page 37

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xr16c2550ip

Manufacturer Part Number
xr16c2550ip
Description
Dual Uart With 16-byte Transmit And Receive Fifos
Manufacturer
Exar Corporation
Datasheet
xr
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
GENERAL DESCRIPTION................................................................................................. 1
PIN DESCRIPTIONS ......................................................................................................... 3
1.0 PRODUCT DESCRIPTION .................................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 7
3.0 UART INTERNAL REGISTERS ........................................................................................................... 15
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 16
5.0 TABLE OF CONTENTS
A
F
ORDERING INFORMATION
EATURES
PPLICATIONS
2.1 CPU INTERFACE ............................................................................................................................................. 7
2.2 DEVICE RESET ................................................................................................................................................ 7
2.3 CHANNEL A AND B SELECTION ................................................................................................................... 7
2.4 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8
2.5 DMA MODE ...................................................................................................................................................... 8
2.6 INTA AND INTB OUTPUTS .............................................................................................................................. 8
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ............................................................................. 9
2.8 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 9
2.9 TRANSMITTER ............................................................................................................................................... 11
2.10 RECEIVER .................................................................................................................................................... 12
2.11 INTERNAL LOOPBACK ............................................................................................................................... 14
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 16
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 16
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 16
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 18
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 19
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 19
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 21
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 22
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 23
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 24
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 24
F
F
F
T
T
T
T
F
F
F
T
F
F
F
F
F
T
T
T
T
T
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 11
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 11
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 12
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 13
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 17
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 17
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 18
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 18
1: C
2: TXRDY#
3: INTA
4: INTA
5: T
6:
7:
8: I
9: R
10: P
1. XR16C2550 B
2. P
3.
4. T
5. E
6. O
7. T
8. T
9. R
10. R
11. I
..................................................................................................................................................... 1
NTERRUPT
UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 15
INTERNAL REGISTERS DESCRIPTION ................................................................................................................... 16
YPICAL DATA RATES WITH A
HANNEL
ECEIVE
XR16C2550 D
IN
YPICAL OSCILLATOR CONNECTIONS
XTERNAL
RANSMITTER
RANSMITTER
ECEIVER
ARITY SELECTION
PERATING
NTERNAL
............................................................................................................................................... 1
ECEIVER
O
AND
AND
UT
FIFO T
A
AND
A
INTB P
INTB P
S
SSIGNMENT
O
C
AND
L
F
O
OURCE AND
PERATION IN NON
LOCK
OOP
RXRDY# O
REQUENCY VERSUS
PERATION IN
O
O
................................................................................................................................ 2
LOCK
RIGGER
B S
PERATION IN NON
PERATION IN
ATA
INS
IN
B
C
........................................................................................................................................................ 21
ACK IN
ELECT
O
ONNECTION FOR
D
B
O
PERATION
..................................................................................................................................................... 2
US
IAGRAM
PERATION FOR
L
P
EVEL
UTPUTS IN
I
RIORITY
............................................................................................................................................... 7
C
NTERCONNECTIONS
FIFO M
14.7456 MH
HANNEL
FIFO M
-FIFO M
......................................................................................................................................... 1
S
F
ELECTION
OR
P
-FIFO M
L
ODE
OWER
EVEL
................................................................................................................................. 9
FIFO
A
R
E
ODE
T
XTENDED
ODE
ECEIVER
AND
RANSMITTER
......................................................................................................................... 13
Z CRYSTAL OR EXTERNAL CLOCK
....................................................................................................................... 18
...................................................................................................................... 12
S
..................................................................................................................... 19
ODE
AND
.................................................................................................................... 13
UPPLY
B ................................................................................................................ 14
................................................................................................................. 7
.............................................................................................................. 12
DMA M
............................................................................................................... 8
D
ATA
C
HART
........................................................................................................ 8
I
R
ODE
ATE
. ............................................................................................. 10
............................................................................................. 8
.......................................................................................... 10
...................................................................... 11
XR16C2550
REV. 1.0.0

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