sc16c654 NXP Semiconductors, sc16c654 Datasheet - Page 17

• Manufacturer Part Number: sc16c654
• Description: Quad Uart With 64-byte Fifo And Infrared Irda Encoder/decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 11617
Product data
same system design. After a hardware reset and during initialization, the
SC16C654/654D sets the default baud rate table according to the state of the
CLKSEL pin. A logic 1 on CLKSEL will set the 1 clock default, whereas logic 0 will
set the 4 clock default table. Following the default clock rate selection during
initialization, the rate tables can be changed by the internal register MCR[7]. Setting
MCR[7] to a logic 1 when CLKSEL is a logic 1 provides an additional divide-by-4,
whereas setting MCR[7] to a logic 0 only divides by 1. (See
Customized Baud Rates can be achieved by selecting the proper divisor values for
the MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 7
7.3728 MHz crystal.
Table 7:
Output baud rate
MCR[7] = 1
50
300
600
1200
2400
4800
9600
19.2 k
38.4 k
57.6 k
115.2 k
Fig 7. Baud rate generator circuitry.
XTAL1
XTAL2
shows the two selectable baud rate tables available when using a
Baud rate generator programming table using a 7.3728 MHz clock
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
MCR[7] = 0
200
1200
2400
4800
9600
19.2 k
38.4 k
76.8 k
153.6 k
230.4 k
460.8 k
OSCILLATOR
CLOCK
LOGIC
Rev. 04 — 19 June 2003
User
16 clock divisor
Decimal
2304
384
192
96
48
24
12
6
3
2
1
DIVIDE-BY-1
DIVIDE-BY-4
LOGIC
LOGIC
HEX
900
180
C0
60
30
18
0C
06
03
02
01
MCR[7] = 0
MCR[7] = 1
SC16C654/654D
DLM
program value
(HEX)
09
01
00
00
00
00
00
00
00
00
00
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
GENERATOR
Table 7
BAUD RATE
LOGIC
and
DLL
program value
(HEX)
00
80
C0
60
30
18
0C
06
03
02
01
Figure
002aaa208
BAUDOUT
17 of 52
7.)