sc16c754bibm NXP Semiconductors, sc16c754bibm Datasheet
sc16c754bibm
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sc16c754bibm Summary of contents
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SC16C754B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 02 — 13 June 2005 1. General description The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow ...
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... Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) Sleep mode 3. Ordering information Table 1: Ordering information Type number Package Name SC16C754BIBM LQFP64 SC16C754BIB80 LQFP80 SC16C754BIA68 PLCC68 9397 750 14668 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Description plastic low profi ...
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Philips Semiconductors 4. Block diagram SC16C754B DATA BUS IOR AND IOW CONTROL RESET LOGIC REGISTER SELECT CSA to CSD LOGIC INTA to INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC INTSEL Fig 1. Block diagram of ...
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... Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 1 CTSA 2 DTRA RTSA 5 INTA 6 7 CSA 8 TXA SC16C754BIBM IOW 9 TXB 10 11 CSB INTB 12 RTSB 13 14 GND 15 DTRB CTSB 16 Rev. 02 — 13 June 2005 SC16C754B 48 ...
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Philips Semiconductors DSRA CTSA DTRA V RTSA INTA CSA TXA IOW TXB CSB INTB RTSB GND DTRB CTSB DSRB Fig 3. Pin configuration for LQFP80 9397 750 14668 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, ...
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Philips Semiconductors Fig 4. Pin configuration for PLCC68 5.2 Pin description Table 2: Pin description Symbol Pin LQFP64 LQFP80 PLCC68 CDA 64 79 CDB 18 23 CDC 31 39 CDD 49 ...
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Philips Semiconductors Table 2: Pin description …continued Symbol Pin LQFP64 LQFP80 PLCC68 CSA 7 9 CSB 11 13 CSC 38 49 CSD 42 53 CTSA 2 4 CTSB 16 18 CTSC 33 44 CTSD 53, ...
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Philips Semiconductors Table 2: Pin description …continued Symbol Pin LQFP64 LQFP80 PLCC68 IOW 20, 21, 22, 27, 40, 41, 42, 60, 61, 62, 80 RESET 27 33 RIA 63 78 RIB 19 24 RIC ...
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Philips Semiconductors Table 2: Pin description …continued Symbol Pin LQFP64 LQFP80 PLCC68 V 4, 21, 6, 46, 66 13, 47, CC 35, 52 XTAL1 25 31 XTAL2 Functional description The SC16C754B UART is pin-compatible with the SC16C554 ...
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Philips Semiconductors 6.2 Hardware flow control Hardware flow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and Auto-RTS can be enabled/disabled independently by programming EFR[7:6]. With Auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates ...
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Philips Semiconductors 6.2.1 Auto-RTS Auto-RTS data flow control originates in the receiver block (see SC16C754B” on page levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level ...
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Philips Semiconductors 6.3 Software flow control Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3: EFR[3] 0 ...
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Philips Semiconductors 6.3.2 TX Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level programmed in TCR[3:0]. Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7:4]. The transmission of ...
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Philips Semiconductors UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RCV FIFO, but assumes the interrupt latency is fairly long. UART1 will continue sending characters until a ...
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Philips Semiconductors 6.5 Interrupts The SC16C754B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. ...
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Philips Semiconductors 6.5.1 Interrupt mode operation In interrupt mode (if any bit of IER[3:0] is ‘1’) the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore not necessary to continuously ...
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Philips Semiconductors 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[ DMA occurs in single character transfers. In DMA ...
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Philips Semiconductors 6.6.2 Block DMA transfers (DMA mode 1) Figure 12 wrptr trigger wrptr Fig 12. TXRDY and RXRDY in DMA mode 1 6.6.2.1 Transmitter TXRDY is active when there is a trigger level number of spaces available. It becomes ...
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Philips Semiconductors 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RX, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the ...
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Philips Semiconductors Table 7: Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 8: Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 ...
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Philips Semiconductors Fig 14. Crystal oscillator connection 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9. Table ...
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Philips Semiconductors Table 10 Table 10: SC16C754B internal registers Register Bit 7 [1] General Register set RHR bit THR bit IER 0/CTS interrupt [2] enable 0 ...
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Philips Semiconductors Remark: Refer to the notes under 7.1 Receiver Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial ...
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Philips Semiconductors 7.3 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. shows FIFO control register bit ...
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Philips Semiconductors 7.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. shows the line control register bit ...
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Philips Semiconductors 7.5 Line Status Register (LSR) Table 13 Table 13: Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of ...
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Philips Semiconductors 7.6 Modem Control Register (MCR) The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 14: Bit [1] MCR[7:5] can only ...
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Philips Semiconductors 7.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from the ...
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Philips Semiconductors 7.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW to HIGH. The INT output ...
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Philips Semiconductors 7.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17: Bit Symbol 7-6 IIR[7:6] 5 IIR[5] 4 IIR[4] 3-1 IIR[3:1] 0 IIR[0] The ...
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Philips Semiconductors 7.10 Enhanced Feature Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. the Enhanced Feature Register bit settings. Table 19: Bit 3:0 7.11 Divisor latches (DLL, DLH) These are ...
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Philips Semiconductors 7.12 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. settings. Table 20: Bit Symbol 7:4 TCR[7:4] 3:0 TCR[3:0] TCR trigger levels are available ...
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Philips Semiconductors The FIFO Rdy register is a read-only register that can be accessed when any of the two UARTs is selected CSA - CSD = 0, MCR[2] (FIFO Rdy Enable logic 1, and loop-back is disabled. The ...
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Philips Semiconductors Table 23: Command set TX FIFO and RX FIFO thresholds to VALUE read FIFO Rdy register set prescaler value to divide-by-1 set prescaler value to divide-by-4 [1] sign here means bit-AND. 9397 750 14668 Product data sheet 5 ...
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Philips Semiconductors 9. Limiting values Table 24: In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg 9397 750 14668 Product data sheet 5 V, 3.3 V and 2.5 ...
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Philips Semiconductors 10. Static characteristics Table 25: Static characteristics Tolerance unless otherwise specified. CC Symbol Parameter Conditions V supply voltage CC V input voltage I V HIGH-level input IH voltage V LOW-level input IL voltage V ...
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Philips Semiconductors 11. Dynamic characteristics Table 26: Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter clock pulse duration oscillator/clock frequency XTAL t address setup time 6s t ...
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Philips Semiconductors 1 ------- [2] Maximum frequency = t 3w [3] RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches. 11.1 Timing diagrams CSx IOW D0 ...
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Philips Semiconductors active IOW RTS change of state DTR CD CTS DSR INT IOR RI Fig 17. Modem input/output timing EXTERNAL CLOCK ------- XTAL t 3w Fig 18. External clock timing 9397 750 14668 Product data sheet ...
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Philips Semiconductors RX INT IOR Fig 19. Receive timing RX RXRDY IOR Fig 20. Receive ready timing in non-FIFO mode 9397 750 14668 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte ...
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Philips Semiconductors RX RXRDY IOR Fig 21. Receive ready timing in FIFO mode TX INT active IOW Fig 22. Transmit timing 9397 750 14668 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with ...
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Philips Semiconductors TX IOW active byte #1 t 27d TXRDY Fig 23. Transmit ready timing in non-FIFO mode TX IOW active byte #32 TXRDY Fig 24. Transmit ready timing in FIFO mode (DMA mode ...
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Philips Semiconductors 12. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original ...
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Philips Semiconductors LQFP80: plastic low profile quad flat package; 80 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT ...
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Philips Semiconductors PLCC68: plastic leaded chip carrier; 68 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT ...
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Philips Semiconductors 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...
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Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...
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Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...
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Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...
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Philips Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...