sc16c754bibm NXP Semiconductors, sc16c754bibm Datasheet - Page 22

• Manufacturer Part Number: sc16c754bibm
• Description: 5 V, 3.3 V And 2.5 V Quad Uart, 5 Mbit/s Max. With 64-byte Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 10:
[1]
[2]
[3]
[4]
9397 750 14668
Product data sheet
A2 A1 A0 Register Bit 7
General Register set
0
0
0
0
0
0
1
1
1
1
1
1
1
Special Register set
0
0
Enhanced Register set
0
1
1
1
1
These registers are accessible only when LCR[7] = 0.
This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
SC16C754B internal registers
RHR
THR
IER
FCR
IIR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
FIFO
Rdy
DLL
DLH
EFR
Xon1
Xon2
Xoff1
Xoff2
[3]
[1]
bit 7
bit 7
0/CTS
interrupt
enable
RX
trigger
level
(MSB)
FCR[0]
DLAB
1 or
1 /4
clock
0/error in
RX FIFO
CD
bit 7
bit 7
bit 7
RX FIFO
D status
bit 7
bit 15
Auto CTS Auto RTS
bit 7
bit 7
bit 7
bit 7
Table 10
[4]
[2]
[2]
lists and describes the SC16C754B internal registers.
Bit 6
bit 6
bit 6
0/RTS
interrupt
enable
RX trigger
level (LSB)
FCR[0]
break
control bit
TCR and
TLR
enable
THR and
TSR empty
RI
bit 6
bit 6
bit 6
RX FIFO
C status
bit 6
bit 14
bit 6
bit 6
bit 6
bit 6
[2]
[2]
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Bit 5
bit 5
bit 5
0/Xoff
0/TX
trigger
level
(MSB)
0/CTS,
RTS
set parity parity type
0/Xon
Any
THR
empty
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
bit 5
bit 13
Special
character
detect
bit 5
bit 5
bit 5
bit 5
Rev. 02 — 13 June 2005
[2]
[2]
[2]
Bit 4
bit 4
bit 4
0/X Sleep
mode
0/TX
trigger
level
(LSB)
0/Xoff
select
0/enable
loop-back
break
interrupt
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
bit 4
bit 12
Enable
enhanced
functions
bit 4
bit 4
bit 4
bit 4
[2]
[2]
[2]
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
interrupt
priority
bit 2
parity
enable
IRQ
enable
OP
framing
error
bit 3
bit 3
bit 3
TX FIFO
D status
bit 3
bit 11
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
CD
Bit 2
bit 2
bit 2
receive
line status
interrupt
TX FIFO
reset
interrupt
priority
bit 1
number of
stop bits
FIFO
ready
enable
parity error overrun
bit 2
bit 2
bit 2
TX FIFO
C status
bit 2
bit 10
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
RI
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Bit 1
bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
interrupt
priority
bit 0
word
length
bit 1
RTS
error
bit 1
bit 1
bit 1
TX FIFO
B status
bit 1
bit 9
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
SC16C754B
DSR
Bit 0
bit 0
bit 0
Rx data
available
interrupt
FIFO
enable
interrupt
status
word
length
bit 0
DTR
data in
receiver
bit 0
bit 0
bit 0
TX FIFO
A status
bit 0
bit 8
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
CTS
Read/
Write
R
W
R/W
W
R
R/W
R/W
R
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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