sc16c852sviet NXP Semiconductors, sc16c852sviet Datasheet - Page 9

• Manufacturer Part Number: sc16c852sviet
• Description: 1.8 V Dual Uart, 20 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And Xscale Vlio Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C852SV_1
Product data sheet
6.4.1 32-byte FIFO mode
6.4.2 128-byte FIFO mode
6.4 FIFO operation
6.5 Hardware flow control
[1]
[2]
[3]
[4]
[5]
[6]
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
First Extra Register Set are empty (0x00) the transmit and receive trigger levels are set by
FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to
the SC16C652B (see
receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be
noted that the user can set the transmit trigger levels by writing to the FCR, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a
time-out function to ensure data is delivered to the external CPU (see
refer to
Table 5.
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register
Set contains any value other than 0x00, the transmit and receive trigger levels are set by
TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit
FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with
granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger
levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
When automatic hardware flow control is enabled, the SC16C852SV monitors the CTSx
pin for a remote buffer overflow indication and controls the RTSx pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTSx transitions from a logic 0 to a logic 1 indicating a flow
control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the
(FCR[7:6, 5:4])
[00, 00]
[01, 01]
[10, 10]
[11, 11]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Second special register are accessible only when EFCR[0] = 1.
Enhanced feature registers are only accessible when LCR = 0xBF.
First extra feature registers are only accessible when EFCR[2:1] = 01b.
Second extra feature registers are only accessible when EFCR[2:1] = 10b.
Table 10
Interrupt trigger level and Flow control mechanism
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
and
INTA/INTB pin activation
RX
8
16
24
28
Rev. 01 — 23 September 2008
Table 11
Table
5), and the FIFO sizes are 32 entries. The transmit and
for the setting of FCR[7:4].
TX
16
8
24
30
Negate RTSA/RTSB
or send Xoff
8
16
24
28
SC16C852SV
Assert RTSA/RTSB
or send Xon
0
7
15
23
Section
© NXP B.V. 2008. All rights reserved.
6.8). Please
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