sc16c852 NXP Semiconductors, sc16c852 Datasheet
sc16c852
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sc16c852 Summary of contents
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... Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C852 with Intel (16 mode) or Motorola (68 mode) bus host interface operates at 2 3.3 V and is available in plastic LQFP48 and very small (Micro-UART) HVQFN32 packages ...
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... Description LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 Rev. 01 — 31 August 2009 SC16C852 1 to allow 16 Version SOT313-2 SOT617-1 5 0.85 mm © NXP B.V. 2009. All rights reserved. ...
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... CSA SELECT CSB POWER- LOWPWR CONTROL INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC16C852 (16 mode) SC16C852_1 Product data sheet Dual UART with 128-byte FIFOs and IrDA encoder/decoder AND LOGIC LOGIC DOWN CLOCK AND BAUD RATE GENERATOR LOGIC XTAL1 Rev. 01 — ...
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... REGISTER SELECT CS POWER- LOWPWR CONTROL IRQ INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 2. Block diagram of SC16C852 (68 mode) SC16C852_1 Product data sheet Dual UART with 128-byte FIFOs and IrDA encoder/decoder AND LOGIC LOGIC DOWN CLOCK AND BAUD RATE GENERATOR LOGIC XTAL1 Rev. 01 — ...
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... CSB Transparent top view terminal 1 index area RXB 4 RXA SC16C852IBS TXA 5 TXB Transparent top view Pin configuration for HVQFN32 Rev. 01 — 31 August 2009 SC16C852 24 RESET 23 RTSA 22 INTA 21 INTB (16 mode 002aad895 24 RESET 23 RTSA 22 ...
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... CSB LOWPWR RXB 4 5 RXA TXRDYB 6 SC16C852IB TXA 7 TXB 8 9 OP2B LOWPWR Pin configuration for LQFP48 Rev. 01 — 31 August 2009 SC16C852 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A 31 RXRDYA (16 mode) 30 INTA 29 INTB n.c. 002aad897 36 RESET 35 ...
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... Clear to Send (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on the CTSx pin indicates the modem or I data set is ready to accept transmit data from the SC16C852. Status can be tested by reading MSR[4]. I Data Set Ready (active LOW). These inputs are associated with individual UART channels, A through B ...
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... After a reset this pin will be set to a logic 1. I Receive data A, B. These inputs are associated with individual serial channel data to the SC16C852 receive input circuits, A through B. The RX signal will logic 1 during reset, idle (no data), or when not receiving data. During the local loopback mode, the RXA/RXB input pin is disabled and TX data is connected to the UART RX input, internally ...
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... Description O Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C852. The TX signal will be a logic 1 O during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TXA/TXB output pin is disabled and TX data is internally connected to the UART RX input ...
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... A low power pin (LOWPWR) is provided to further reduce power consumption by isolating the host bus interface. The SC16C852 is capable of operation Mbit/s with an external 80 MHz clock. With a crystal, the SC16C852 is capable of operation up to 1.5 Mbit/s. The rich feature set of the SC16C852 is available through internal registers. These ...
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... UART A-B functions The UART provides the user with the capability to bidirectionally transfer information between an external CPU, the SC16C852 package, and an external serial device. A logic 0 (LOW) on chip select pins CSA and/or CSB allows the user to configure, send data, and/or receive data via UART channels A, B. Individual channel select functions are shown in Table 3 ...
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... NXP Semiconductors 6.3 Internal registers The SC16C852 provides two sets of internal registers (A and B) consisting of 25 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR) ...
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... EFR[7] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C852 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTSx input returns to a logic 0, indicating more data may be sent ...
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... FIFO. When using software flow control, the Xon/Xoff characters cannot be used for data transfer. In the event that the receive buffer is overfilling, the SC16C852 automatically sends an Xoff character (when enabled) via the serial TX output to the remote UART. The ...
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... Interrupt priority and time-out interrupts The interrupts are enabled by IER[7:0]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit the SC16C852 will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR indicates the current singular highest priority interrupt only ...
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... The generator divides the input 16 clock by any divisor from SC16C852 divides the basic external clock by 16. The baud rate is configured via the CLKPRES, DLL and DLM internal register functions. Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of the baud rate generator ...
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... Rev. 01 — 31 August 2009 SC16C852 XTAL1 XTAL2 1 1.8432 MHz 002aaa870 XTAL1 XTAL2 002aac630 DLM DLL program value program value (hexadecimal) (hexadecimal ...
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... NXP Semiconductors 6.10 DMA operation The SC16C852 FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYA/RXRDYB and TXRDYA/TXRDYB output pins ...
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... REGISTERS REGISTER FLOW CONTROL LOGIC MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 01 — 31 August 2009 SC16C852 TXA, TXB IR ENCODER RXA, RXB IR DECODER RTSA, RTSB CTSA, CTSB DTRA, DTRB DSRA, DSRB (OP1A, OP1B) RIA, RIB (OP2A, OP2B) CDA, CDB 002aad899 © ...
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... Low power feature A low power feature is provided by the SC16C852 to prevent the switching of the host data bus from influencing the sleep current. When the pin LOWPWR is activated (logic HIGH), the device immediately and unconditionally goes into Low power mode. All clocks are stopped and most host interface pins are isolated to reduce power consumption ...
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... ID address, the controller takes no further action, and the receiver will receive the subsequent data. SC16C852_1 Product data sheet Dual UART with 128-byte FIFOs and IrDA encoder/decoder Rev. 01 — 31 August 2009 SC16C852 © NXP B.V. 2009. All rights reserved ...
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... Register descriptions Table 10 assigned bit functions are more fully defined in SC16C852_1 Product data sheet Dual UART with 128-byte FIFOs and IrDA encoder/decoder details the assigned bit functions for the SC16C852 internal registers. The Rev. 01 — 31 August 2009 SC16C852 Section 7.1 through Section 7.23. © ...
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... Table 10. SC16C852 internal registers [ Register Default Bit 7 [2] General register set RHR XX bit THR XX bit IER 00 CTS [3] interrupt FCR 00 RCVR trigger (MSB ISR 01 FIFOs enabled LCR 00 divisor latch enable MCR ...
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... Table 10. SC16C852 internal registers …continued [ Register Default Bit 7 [6] Enhanced feature register set EFR 00 Auto CTS Xon1 00 bit Xon2 00 bit Xoff1 00 bit Xoff2 00 bit 15 [7] First extra feature register set ...
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... CTSA/CTSB pin transitions from a logic logic 1. RTS interrupt. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt. The SC16C852 issues an interrupt when the RTSA/RTSB pin transitions from a logic logic 1. Xoff interrupt. logic 0 = disable the software flow control, receive Xoff interrupt (normal ...
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... ISR loading the THR with new data characters. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, setting IER[3:0] puts the SC16C852 in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status ...
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... Once active, the TXRDYA/TXRDYB pin will logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode ‘0’: When the SC16C852 is in non-FIFO mode the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDYA/RXRDYB pin will be a logic 0 ...
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... FIFO is completely full; see operation”. It will be a logic 0 when the trigger level has been reached. Receive operation in mode ‘1’: When the SC16C852 is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached Receive Time-Out has occurred, the RXRDYA/RXRDYB pin will logic 0 ...
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... NXP Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C852 provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... LCR[2] stop bit length Word length (bits) Stop bit length (bit times LCR[1:0] word length LCR[0] Word length (bits Rev. 01 — 31 August 2009 SC16C852 Table 18). Table 19). Table 20). © NXP B.V. 2009. All rights reserved ...
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... OP2A/OP2B to a logic 0 Remark: OP2A/OP2B pins do not exist on the HVQFN32 package. MCR[2] OP1A/OP1B are not available as an external signal in the SC16C852. This bit is instead used in the Loopback mode only. In the Loopback mode, this bit is used to write the state of the modem RI interface signal. ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C852 and the CPU. Table 22. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C852_1 Product data sheet Dual UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... A modem Status Interrupt will be generated. [1] MSR[2] RI logic change (normal default condition) logic 1 = the RI input to the SC16C852 has changed from a logic logic 1. A modem Status Interrupt will be generated. [1] MSR[1] DSR logic DSR change (normal default condition) logic 1 = the DSR input to the SC16C852 has changed state since the last time it was read ...
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... Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can only be accessed if EFCR[2:1] are zeroes. 7.10 Scratchpad Register (SPR) The SC16C852 provides a temporary data register to store 8 bits of user information. 7.11 Division Latch (DLL and DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLM, stores the most signifi ...
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... Special Character Detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. The SC16C852 compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software fl ...
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... This register stores the programmable receive interrupt trigger levels for 128-byte FIFO mode 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 Rev. 01 — 31 August 2009 SC16C852 [1] [1] . [1] . © NXP B.V. 2009. All rights reserved ...
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... Section 7.3. Clock Prescaler register bits description Symbol Description CLKPRES[7:4] reserved CLKPRES[3:0] Clock Prescaler value. Reset to 0. Rev. 01 — 31 August 2009 SC16C852 Table 29 shows FLWCNTH register [1] Table 30 shows FLWCNTL register bit [1] © NXP B.V. 2009. All rights reserved ...
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... AFCR2[1] RXDisable. Disable receiver logic 0 = receiver is enabled logic 1 = receiver is disable AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode logic logic 0 = normal RS-232 mode logic 1 = enable 9-bit mode Rev. 01 — 31 August 2009 SC16C852 © NXP B.V. 2009. All rights reserved ...
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... FIFO falls below the trigger level, or becomes empty and the last stop bit has been shifted out of the Transmit Shift Register. Rev. 01 — 31 August 2009 SC16C852 [1] © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 7.23 SC16C852 external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 35. Table 35. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon1 Xon2 ...
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... DD Conditions except XTAL1 clock except XTAL1 clock 800 A OH LOW-level HIGH-level MHz Rev. 01 — 31 August 2009 SC16C852 Min - Min Max Min 0.3 +0.45 0.3 1 ...
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... Dual UART with 128-byte FIFOs and IrDA encoder/decoder 10 %; unless otherwise specified. DD Conditions [1][ load 25 pF load [ load 25 pF load 25 pF load [ load [ load [ load 25 pF load Rev. 01 — 31 August 2009 SC16C852 Min Max Min Max 12 ...
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... RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. SC16C852_1 Product data sheet Dual UART with 128-byte FIFOs and IrDA encoder/decoder 10 %; unless otherwise specified. DD Conditions [1][ load 25 pF load 25 pF load 25 pF load [3][4] Rev. 01 — 31 August 2009 SC16C852 Min Max Min ...
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... SC16C852_1 Product data sheet Dual UART with 128-byte FIFOs and IrDA encoder/decoder t h(A) valid address t h(IOW-CS) active t t w(IOW) d(IOW) active t h(IOWH-D) t su(D-IOWH) data t h(A) t w(CS) t h(CS-RWH) t h(CSH-D) t su(D-CSH) Rev. 01 — 31 August 2009 SC16C852 002aac405 t d(RW) 002aac408 © NXP B.V. 2009. All rights reserved ...
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... Dual UART with 128-byte FIFOs and IrDA encoder/decoder t h(A) valid address t h(IOR-CS) active t t w(IOR) d(IOR) active t d(IOR-Q) t dis(IOR-QZ) data t h( w(CS) d(CS) t dis(CS-QZ) t d(CS- w(clk) Rev. 01 — 31 August 2009 SC16C852 002aac406 002aac407 002aac357 © NXP B.V. 2009. All rights reserved ...
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... Figure 10. Figure 12. Rev. 01 — 31 August 2009 SC16C852 change of state t d(modem-INT) active active t d(IOR-INTL) active active t d(modem-INT) change of state 002aac611 change of state t d(modem-IRQL) active active t d(CS-IRQH)R ...
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... data bits 6 data bits 7 data bits 16 baud rate clock Rev. 01 — 31 August 2009 SC16C852 next data parity stop start bit bit bit d(stop-INT) active t d(IOR-INTL) ...
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... Dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit data bits ( start bit data bits ( Rev. 01 — 31 August 2009 SC16C852 next data parity stop start bit bit bit d(stop-RXRDY) active data ready t d(IOR-RXRDYH) active ...
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... Dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit data bits ( start bit data bits ( Rev. 01 — 31 August 2009 SC16C852 parity stop bit bit first byte that reaches the trigger level t d(stop-RXRDY) active data ready t d(IOR-RXRDYH) active ...
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... data bits 6 data bits 7 data bits t d(start-IRQL) 16 baud rate clock Rev. 01 — 31 August 2009 SC16C852 next data parity stop start bit bit bit d(IOW-INTL) active 002aac616 next data ...
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... d(start-TXRDY) t d(CS-TXRDYH)W transmitter not ready Rev. 01 — 31 August 2009 SC16C852 next data start parity stop bit bit bit active transmitter ready next data parity stop start bit bit ...
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... data bits 6 data bits 7 data bits t d(start-TXRDY) t d(CS-TXRDYH)W trigger lead Rev. 01 — 31 August 2009 SC16C852 parity stop bit bit 002aac615 parity stop bit bit 002aac624 © NXP B.V. 2009. All rights reserved. ...
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... Dual UART with 128-byte FIFOs and IrDA encoder/decoder UART frame start bit time bit time start Rev. 01 — 31 August 2009 SC16C852 data bits bit time clock delay data bits UART frame © ...
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... 2.5 scale (1) ( 0.27 0.18 7.1 7.1 9.15 9.15 0.5 0.17 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 31 August 2009 SC16C852 detail 0.75 0.95 1 0.2 0.12 0.1 0.45 0.55 EUROPEAN PROJECTION SOT313 ( ...
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... 2.5 scale (1) ( 5.1 3.25 5.1 3.25 0.5 3.5 4.9 2.95 4.9 2.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 31 August 2009 SC16C852 detail 0.5 0.05 0.1 3.5 0.1 0.05 0.3 EUROPEAN PROJECTION SOT617 ISSUE DATE 01-08-08 02-10-18 © NXP B.V. 2009. All rights reserved. ...
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... Solder bath specifications, including temperature and impurities SC16C852_1 Product data sheet Dual UART with 128-byte FIFOs and IrDA encoder/decoder Rev. 01 — 31 August 2009 SC16C852 © NXP B.V. 2009. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 32. Rev. 01 — 31 August 2009 SC16C852 Figure 32) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2009. All rights reserved. ...
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... Integrated Service Digital Network Least Significant Bit Most Significant Bit Printed-Circuit Board Restriction of Hazardous Substances directive Universal Asynchronous Receiver/Transmitter Data sheet status Product data sheet Rev. 01 — 31 August 2009 SC16C852 peak temperature Change notice Supersedes - - © NXP B.V. 2009. All rights reserved. time ...
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... Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 31 August 2009 SC16C852 © NXP B.V. 2009. All rights reserved ...
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... Flow Control Trigger Level Low (FLWCNTL 7.19 Clock Prescaler (CLKPRES 7.20 RS-485 turn-around time delay (RS485TIME) 38 7.21 Advanced Feature Control Register 2 (AFCR2 7.22 Advanced Feature Control Register 1 (AFCR1 7.23 SC16C852 external reset condition and software reset Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 41 9 Static characteristics . . . . . . . . . . . . . . . . . . . 41 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 42 10.1 Timing diagrams Package outline . . . . . . . . . . . . . . . . . . . . . . . . 54 12 Soldering of SMD packages ...