sc16c2552b NXP Semiconductors, sc16c2552b Datasheet - Page 12

• Manufacturer Part Number: sc16c2552b
• Description: Sc16c2552b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7. Register descriptions
Table 6:
[1]
[2]
[3]
9397 750 14442
Product data
A2
General Register Set
0
0
0
0
0
0
1
1
1
1
Special Register Set
0
0
0
The value shown in represents the register’s initialized HEX value; X = n/a.
The General Register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 0.
The Baud Rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 1.
Set A is accessible when CHSEL is a logic 1, and Set B is accessible when CHSEL is a logic 0.
A1
0
0
0
1
1
1
0
0
1
1
0
0
1
A0
0
0
1
0
0
1
0
1
0
1
0
1
0
SC16C2552B internal registers
Register
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
AFR
[3]
[2]
Default
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
00
Table 6
assigned bit functions are further defined in
[1]
details the assigned bit functions for the SC16C2552B internal registers. The
Bit 7
bit 7
bit 7
0
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
CD
bit 7
bit 7
bit 15
bit 7
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 02 — 13 December 2004
Bit 6
bit 6
bit 6
0
RCVR
trigger
(LSB)
FIFOs
enabled
set
break
0
THR and
TSR
empty
RI
bit 6
bit 6
bit 14
bit 6
Bit 5
bit 5
bit 5
0
0
0
set
parity
0
THR
empty
DSR
bit 5
bit 5
bit 13
bit 5
Bit 4
bit 4
bit 4
0
0
0
even
parity
loop
back
break
interrupt
CTS
bit 4
bit 4
bit 12
bit 4
Section 7.1
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
OP2
output
control
framing
error
bit 3
bit 3
bit 11
bit 3
CD
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
through
Bit 2
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits word
OP1
parity
error
bit 2
bit 2
bit 10
bit 2
SC16C2552B
RI
Section
bit 1
bit 1
bit 1
bit 1
bit 1
Bit 1
transmit
holding
register
interrupt
RCVR
FIFO
reset
INT
priority
bit 0
length
bit 1
RTS
overrun
error
bit 9
DSR
7.11.
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
bit 0
CTS
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