sc16c2552b NXP Semiconductors, sc16c2552b Datasheet - Page 9

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sc16c2552b

Manufacturer Part Number
sc16c2552b
Description
Sc16c2552b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos
Manufacturer
NXP Semiconductors
Datasheet

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Product data
design. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for
the MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 5
external clock input.
Table 5:
Output
baud rate
50
75
150
300
600
1200
2400
4800
7200
9600
19.2 k
38.4 k
57.6 k
115.2 k
Fig 3. Crystal oscillator connection.
shows the selectable baud rate table available when using a 1.8432 MHz
Baud rate generator programming table using a 1.8432 MHz clock
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Output
16 clock divisor
(decimal)
2304
1536
768
384
192
96
48
24
16
12
6
3
2
1
Rev. 02 — 13 December 2004
User
16 clock divisor
(HEX)
900
600
300
180
C0
60
30
18
10
0C
06
03
02
01
1.8432 MHz
C1
22 pF
Y1
C2
33 pF
002aaa125
DLM
program value
(HEX)
09
06
03
01
00
00
00
00
00
00
00
00
00
00
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C2552B
DLL
program value
(HEX)
00
00
00
80
C0
60
30
18
10
0C
06
03
02
01
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