sc16c2552b NXP Semiconductors, sc16c2552b Datasheet - Page 13

• Manufacturer Part Number: sc16c2552b
• Description: Sc16c2552b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14442
Product data
7.1 Transmit (THR) and Receive (RHR) Holding Registers
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
flag in the LSR[5] register will be set to a logic 1 when the transmitter is empty or
when data is transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and
a Receive Serial Shift Register (RSR). Receive data is removed from the
SC16C2552B and receive FIFO by reading the RHR register. The receive section
provides a mechanism to prevent false starts. On the falling edge of a start or false
start bit, an internal receiver counter starts counting clocks at the 16 clock rate. After
7-
time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start
bit in this manner prevents the receiver from assembling a false character. Receiver
status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
Table 7:
Bit
7-4
3
2
1
1
2
clocks, the start bit time should be shifted to the center of the start bit. At this
Interrupt Enable Register bits description
Symbol
IER[7-4]
IER[3]
IER[2]
IER[1]
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 02 — 13 December 2004
Description
Not used; initialized to logic 0.
Modem Status Interrupt. This interrupt will be issued whenever
there is a modem status change as reflected in MSR[0-3].
Receive Line Status interrupt. This interrupt will be issued
whenever a receive data error condition exists as reflected in
LSR[1-4].
Transmit Holding Register interrupt. In the 16C450 mode, this
interrupt will be issued whenever the THR is empty, and is
associated with LSR[5]. In the FIFO modes, this interrupt will be
issued whenever the FIFO and THR are empty.
Logic 0 = Disable the modem status register interrupt (normal
default condition).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable the receiver line status interrupt (normal
default condition).
Logic 1 = Enable the receiver line status interrupt.
Logic 0 = Disable the Transmit Holding Register Empty (TXRDY)
interrupt (normal default condition).
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C2552B
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