spear-09-h122 STMicroelectronics, spear-09-h122 Datasheet - Page 30
spear-09-h122
Manufacturer Part Number
spear-09-h122
Description
Spear Tm Head600
Manufacturer
STMicroelectronics
Datasheet
1.SPEAR-09-H122.pdf
(37 pages)
- Current page: 30 of 37
- Download datasheet (330Kb)
Main Blocks
4.7
4.8
30/37
USB2 Device Controller
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Low jitter PLL
Within the USB Hosts and device a local Low Jitter PLL is provided to meet the USB2.0
specification requirements.
It supports the 480 Mbps high-speed (HS) for USB 2.0, as well as the 12 Mbps full-
speed (FS) and the low-speed (LS) for USB 1.1.
It supports 16 physical endpoints and proper configurations to achieve logical
endpoints.
Integrated USB transceiver (PHY)
Local FIFO having size of 4 Kbyte shared among all the endpoints.
Both DMA mode and Slave-Only mode supported.
In DMA mode, the UDC supports descriptor-based memory structures in application
memory.
In both modes, an AHB slave is provided by UDC-AHB, acting as programming
interface to access to memory-mapped control and status registers (CSRs);
An AHB master for data transfer to system memory is provided, supporting 8, 16, and
32-bit wide data transactions on the AHB bus.
A USB Plug Detect (UPD) which detects the connection of a cable.
EP0
EP1~15
Control (IN/OUT)
Software configurable to:
– Bulk In
– Bulk Out
– Interrupt In
– Interrupt Out
– Isochronous.
SPEAR-09-H122
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