spear-09-h122 STMicroelectronics, spear-09-h122 Datasheet - Page 7

• Manufacturer Part Number: spear-09-h122
• Description: Spear Tm Head600
• Manufacturer: STMicroelectronics

SPEAR-09-H122
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1.1
Product Overview
An outline picture of the main SPEAr Head600 functional interfaces is shown in
Figure 1.
Features
The following main functionalities are implemented in the SPEAr Head600 SoC device:
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ARM926EJ-S core @333MHz, 16KB-I/D cache, configurable TMC-I/D size, MMU, TLB,
JTAG and ETM trace module (multiplexed interfaces).
600KByte reconfigurable logic array (programmable through 4Metal and 4Vias).
128KByte configurable internal memory pool (Single and Dual port memory).
32KByte Rom (code customizable) 8KByte common SRam.
Dynamic Power save features.
High performance linked list 8 channels DMA.
Ethernet GMII/MII (IEEE802.3/3x/1Q), management i/f.
USB2.0 Device (High-Full-Slow speed); integrated PHY transceiver.
2-USB2.0 Host (High-Full-Slow speed); integrated PHY transceiver.
Ext. memory i/f: 8/16bit DDR1@200Mhz/DDR2@333Mhz.
Flash interface: Nand 8/16bit and Serial (up to 50Mbps).
3-SPI Master/Slave (Motorola-Texas-National) up to 40Mbps.
I
2-Uart (speed rate up to 460.8Kbps).
IrDA (Fir-Mir-Sir) from 9.6Kbps to 4Mbps speed-rate.
Color LCD up to 1024x768 resolutions; 24bpp true colour; STN/TFT display panel.
10 GPIOs bidirectional signals with interrupt capability.
9 LVDS (8 out and 1 input) signals; customizable interface through programmable logic.
88 RAS-GPIOs user customizable bidirectional signals (up to 4 clocks).
2
C (High-Fast-Slow speed) Master/Slave.
Main SPEAr Head600 functional interfaces
GMII/MII
USB2.0 dev
USB2.0 host(2)
CLCD
DDR 1/2
PL_GPIOs
PL_LVDSs
JTAG & Test
I2C
SPIs (3)
UARTs (2)
IrDA
GPIOs
ADCs
Flash Serial
Flash Nand
Product Overview
Figure
1.
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