spear-09-h122 STMicroelectronics, spear-09-h122 Datasheet - Page 31

• Manufacturer Part Number: spear-09-h122
• Description: Spear Tm Head600
• Manufacturer: STMicroelectronics

SPEAR-09-H122
4.9
4.9.1
4.9.2
4.9.3
Reconfigurable logic array
Overview
The Configurable Logic array consists of an embedded macro where it is possible to
implement a custom project by mapping up to 600K equivalent gates.
This macro is interfaced with the rest of the system by some AHB bus, some memory
channels and has a direct connection to the 1st ARM processor internal bus. In this way is
also possible to customize the TCM memory or add a coprocessor using this macro.
The following memory cuts are available to this block:
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The array is also connected to 88 I/O (3.3V capable/tolerant and 4 mA sink/source) plus 9
lvds lines (one input and 8 outputs).
The following clocks can be used in the integrated logic:
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Custom project development
The flow to develop a custom project to embed in the SPEAr Head600 is similar to the
standard ASIC flow.
The Configurable Logic is an empty module of the whole System on Chip. Pin out and
maximum gates are fixed. The HDL project is synthesized using dedicated library and post
synthesis simulation is possible to verify the custom net-list.
Regarding the back end flow, after the place and route phase the verification procedure is
the same as a standard ASIC flow.
Customization process
The layers used for the IP configuration range from 2 metals - 1 via up to 4 metals - 4 vias.
Diffusion and remaining metal/vias are invariant across multiple custom designs. Density
and performance scale with number of customization layers.
The Configurable Logic included in the SPEAr Head600 Chip is a 600Kgates equivalent
array when customized using 4 metals - 4 vias.
4 cuts single port with size of 8kB each
8 cuts single port with size of 4kB each
16 cuts single port with size of 2kB each
8 cuts dual port with size of 2kB each
4 cuts dual port with size of 4kB each
5 different coming from the external balls
4 different coming from the integrated frequency synthesizer
PLL1 frequency
PLL2 Frequency
48 MHz (USB PLL)
30 MHZ (MAIN Oscillator)
32.768 KHz (RTC Oscillator)
APB clock (programmable)
AHB clock (programmable)
Main Blocks
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