wm8569seds-v Wolfson Microelectronics plc, wm8569seds-v Datasheet - Page 19

• Manufacturer Part Number: wm8569seds-v
• Description: 24-bit, 192khz Stereo Codec With Volume Control
• Manufacturer: Wolfson Microelectronics plc

Production Data
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RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN is sampled by the WM8569 on the rising edge of DACBCLK
preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the
falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. LRC are high during the left samples and low during the right samples (Figure 14).
Figure 14 Right Justified Mode Timing Diagram
I
In I
following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the
first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising
edge of ADCBCLK. LRC are low during the left samples and high during the right samples.
Figure 15 I
DSP MODE A
In DSP mode A, the MSB of DAC left channel data is sampled by the WM8569 on the second rising
edge on DACBCLK following a DACLRC rising edge. DAC right channel follows DAC left channel
(Figure 16).
Figure 16 DSP Mode A Timing Diagram – DAC Data Input
2
DIN1/2/3/
DACBCLK/
DIN1/2/3/
ADCBCLK
S MODE
DACLRC/
DACLRC/
DACBCLK/
ADCLRC
ADCBCLK
ADCLRC
DOUT
DOUT
2
S mode, the MSB of DIN is sampled by the WM8569 on the second rising edge of DACBCLK
2
S Mode Timing Diagram
MSB
1 BCLK
1
2
MSB
1
3
LEFT CHANNEL
LEFT CHANNEL
2
3
n-2 n-1
n-2 n-1
n
LSB
n
LSB
1/fs
1/fs
MSB
1 BCLK
1
2
MSB
1
3
RIGHT CHANNEL
RIGHT CHANNEL
2
3
n-2 n-1
PD Rev 4.0 June 2006
n-2 n-1
n
LSB
WM8569
n
LSB
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