wm8569seds-v Wolfson Microelectronics plc, wm8569seds-v Datasheet - Page 23

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wm8569seds-v

Manufacturer Part Number
wm8569seds-v
Description
24-bit, 192khz Stereo Codec With Volume Control
Manufacturer
Wolfson Microelectronics plc
Datasheet
Production Data
CONTROL INTERFACE REGISTERS
w
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both the left
and right channel of the DAC from the next audio input sample. No update to the attenuation
registers is required for ATC to take effect.
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function:
With IZD enabled, applying 1024 consecutive zero input samples each stereo channel will cause that
stereo channel outputs to be muted to V
receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right input to the audio Interface are
applied to the left and right DAC:
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
DAC Channel Control
DAC Channel Control
DAC Control
0000010
0000010
0000010
BIT
BIT
BIT
8:5
3
4
LABEL
LABEL
LABEL
PL[3:0]
ATC
IZD
MID
. Mute will be removed as soon as that stereo channel
DEFAULT
DEFAULT
DEFAULT
1001
0
0
Attenuator Control Mode:
Infinite Zero Mute Enable
PL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0: Right channel use right
1: Right channel use left
0 : Disable inifinite zero mute
1: Enable infinite zero mute
attenuations
attenuations
DESCRIPTION
DESCRIPTION
DESCRIPTION
Left
Output
Mute
Left
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
PD Rev 4.0 June 2006
WM8569
Right
Output
Mute
Mute
Mute
Mute
Left
Left
Left
Left
Right
Right
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
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