wm8569seds-v Wolfson Microelectronics plc, wm8569seds-v Datasheet - Page 24

• Manufacturer Part Number: wm8569seds-v
• Description: 24-bit, 192khz Stereo Codec With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8569
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DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the DACFMT[1:0] register bits:
In left justified, right justified or I
If this bit is set high, the expected polarity of DACLRC will be the opposite of that shown Figure 13,
Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and right
channels, a 1 sample phase difference will be introduced. In DSP modes, the DACLRP register bit is
used to select between modes A and B.
The DACIWL[1:0] bits are used to control the input word length.
Note: 32-bit right justified mode is not supported.
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8569 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I
minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC channels.
By default, DACLRC and DIN are sampled on the rising edge of DACBCLK and should ideally
change on the falling edge. Data sources that change DACLRC and DIN on the rising edge of
DACBCLK can be supported by setting the DACBCP register bit. Setting DACBCP to 1 inverts the
polarity of DACBCLK to the inverse of that shown in Figure 13 to Figure 19.
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
Interface Control
Interface Control
Interface Control
Interface Control
0000011
0000011
0000011
0000011
2
S mode, any width of 24 bits or less is supported provided that LRC is high for a
BIT
1:0
BIT
BIT
BIT
5:4
2
3
2
S modes, the DACLRP register bit controls the polarity of DACLRC.
DACFMT
DACBCP
DACLRP
DACIWL
LABEL
LABEL
LABEL
LABEL
[1:0]
[1:0]
DEFAULT
DEFAULT
DEFAULT
DEFAULT
0
00
00
0
In left/right/I
DACLRC Polarity (normal)
In DSP Mode:
Interface Format Select:
DACBCLK Polarity (DSP Modes):
Input Word Length:
00 : Right justified mode
01: Left justified mode
10: I
11: DSP mode A orB
0 : Normal DACLRC polarity
1: Inverted DACLRC polarity
0 : Mode A
1: Mode B
0: Normal BCLK polarity
1: Inverted BCLK polarity
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
2
S mode
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
2
S Modes:
PD Rev 4.0 June 2006
Production Data
24