wm8569seds-v Wolfson Microelectronics plc, wm8569seds-v Datasheet - Page 28

• Manufacturer Part Number: wm8569seds-v
• Description: 24-bit, 192khz Stereo Codec With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8569
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ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
MUTE PIN DECODE
The MUTE pin can either be used an output or an input. As an output it indicated 1024 consecutive
zero samples to the DAC. By default selecting the MUTE to represent if the DAC has received more
than 1024 midrail samples will cause the MUTE to be asserted as a softmute on the DAC. Disabling
the decode block will cause any logical high on the MUTE pin to apply a softmute to the DAC.
In left justified, right justified or I
If this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown in Figure
13, Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and
right channels, a 1 sample phase difference will be introduced. In DSP modes, the ADCLRP register
bit is used to select between modes A and B.
By default, ADCLRC and DOUT are sampled on the rising edge of ADCBCLK and should ideally
change on the falling edge. Data sources that change ADCLRC and DOUT on the rising edge of
ADCBCLK can be supported by setting the ADCBCP register bit. Setting ADCBCP to 1 inverts the
polarity of ADCBCLK to the inverse of that shown in Figure 13 to Figure 19
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
Interface Control
Interface Control
ADC Control
ADC Control
0001100
0001100
0001100
0001100
BIT
BIT
BIT
BIT
3
4
5
6
2
S modes, the ADCLRP register bit controls the polarity of ADCLRC.
ADCHPD
ADCBCP
ADCLRP
LABEL
LABEL
LABEL
MPD
LABEL
DEFAULT
DEFAULT
DEFAULT
DEFAULT
0
0
0
0
ADC Highpass Filter Disable:
ADCBCLK Polarity (DSP Modes):
MUTE Pin Decode Disable:
In Left/Right/I
ADCLRC Polarity (normal)
In DSP Mode:
0: normal BCLK polarity
1: inverted BCLK polarity
0: Highpass filter enabled
1: Highpass filter disabled
0: MUTE pin decode enable
1: MUTE pin decode disable
0: normal DACLRC polarity
1: inverted DACLRC polarity
0: DSP mode A
1: DSP mode B
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
PD Rev 4.0 June 2006
2
S Modes:
Production Data
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