isppac-clk5620v-01t48c Lattice Semiconductor Corp., isppac-clk5620v-01t48c Datasheet - Page 20

• Manufacturer Part Number: isppac-clk5620v-01t48c
• Description: In-system Programmable, Zero-delay Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 14. LVCMOS/LVTTL Input Receiver Configuration
HSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input
pair. The ‘-’ input terminal should be tied to the appropriate V
terminal should be tied to a V
set to 50 . Figure 15 shows an appropriate configuration. Refer to the “Recommended Operating Conditions -
Supported Logic Standards” table in this data sheet for suitable values of V
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 15. SSTL2, SSTL3, HSTL Receiver Configuration
VTT
TT
Signal In
VREF IN
Signal In
termination supply. The positive input’s terminating resistor should be engaged and
No Connect
No Connect
REFVTT
REFA+
REFA-
REFVTT
REFA+
REFA-
ispClock5600
50
ispClock5600
R
CLOSED
T
OPEN
20
OPEN
REF
value, and the associated REFVTT or FBKVTT
Differential
Receiver
ispClock5600 Family Data Sheet
Single-ended
Receiver
REF
and V
TT.