isppac-clk5620v-01t48c Lattice Semiconductor Corp., isppac-clk5620v-01t48c Datasheet - Page 22

• Manufacturer Part Number: isppac-clk5620v-01t48c
• Description: In-system Programmable, Zero-delay Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispClock5600 Family Data Sheet
Note that while a floating 100
resistor forms a complete termination for an LVDS signal line, additional circuitry
may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out-
put driver typically requires an external DC ‘pull-down’ path to a V
termination voltage (typically VCC-2V) to
TERM
properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5600’s inter-
nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive
current. The pull-down should be implemented with external resistors placed close to the LVPECL driver
(Figure 18)
Figure 18. LVPECL Input Receiver Configuration
ispClock5600
Differential
+Signal In
Receiver
REFA+
LVPECL
Driver
-Signal In
REFA-
R
R
50
50
PD
PD
CLOSED
CLOSED
V
No Connect
TERM
REFVTT
Please note that while the above discussions specify using 50
termination impedances, the actual impedance
required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. The
actual impedance required will be a function of the driver used to generate the signal and the transmission medium
used (PCB traces, connectors and cabling). The ispClock5600’s ability to adjust input impedance over a range of
40 to 70 allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to
swap out components.
Output Drivers
The ispClock5600 provide banks of configurable, internally-terminated high-speed dual-output line drivers. The
ispClock5610 provides five driver banks, while the ispClock5620 provides ten. Each of these driver banks may be
configured to provide either a single differential output signal, or a pair of single-ended output signals. Programma-
ble internal source-series termination allows the ispClock5600 to be matched to transmission lines with imped-
2
ances ranging from 40 to 70 Ohms. The outputs may be independently enabled or disabled, either from E
CMOS
configuration or by external control lines. Additionally, each can be independently programmed to provide a fixed
amount of signal delay or skew, allowing the user to compensate for the effects of unequal PCB trace lengths or
loading effects. Figure 19 shows a block diagram of a typical ispClock5600 output driver bank and associated skew
control.
Because of the high edge rates which can be generated by the ispClock5600’s clock output drivers, the VCCO
power supply pin for each output bank should be individually bypassed. Low ESR capacitors with values ranging
from 0.01 to 0.1 µF may be used for this purpose. Each bypass capacitor should be placed as close to its respec-
tive output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated
parasitic inductances.
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